Design-for-test, logic built-in self-test, memory technology mapping, and clocking concerns require team-months of verification time as they traditionally happen at gate-level. We present a novel concern-oriented methodology that enables automatic insertion of these concerns at the register-transfer-level where verification is easier. The methodology involves three main phases: 1) flipflop inference and instantiation algorithms that handle parametric register transfer level (RTL) modules; 2) transformations that take entry RTL and produce RTL modules where memory elements are separated from functionality; and 3) a concern weaving tool that automatically inserts memory related design concerns implemented in recipe files into the RTL modules. The transformation is sound as proven and validated by equivalence checking using formal verification. We implemented the methodology in a tool that is currently used in an industrial setting wherein it reduced design verification time by more than 40%. The methodology is also effective with open source embedded system frameworks.

Article Free Access Share on A new time-domain macromodel for transient simulation of uniform/nonuniform multiconductor transmission-line interconnections Authors: Monjurul Haque University of Iowa, Iowa City, IA University of Iowa, Iowa City, IAView Profile , Ali El-Zein IBM, Poughkeepsie, NY and University of Iowa, Iowa City, IA IBM, Poughkeepsie, NY and University of Iowa, Iowa City, IAView Profile , S. Chowdhury Motorola, Austin, TX and University of Iowa, Iowa City, IA Motorola, Austin, TX and University of Iowa, Iowa City, IAView Profile Authors Info & Claims DAC '94: Proceedings of the 31st annual Design Automation ConferenceJune 1994 Pages 628–633https://doi.org/10.1145/196244.196596Published:06 June 1994Publication History 4citation219DownloadsMetricsTotal Citations4Total Downloads219Last 12 Months3Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

This paper extends the time-domain modal analysis for simulating transmission lines to include lossy coupled systems of arbitrary geometries. It provides exact solution for the case where the dielectric medium is homogeneous and an approximate one for the case of an inhomogeneous medium. A numerical example is given, illustrating the accuracy of the proposed method.>

A method of characteristics solution of a nonuniform transmission line having frequency-dependent per-unit-length parameters is formulated. The method, in general, requires the use of FFT to incorporate the frequency-dependent components of the distributed parameters in the time-domain equations. For skin-effect frequency-dependence, an analytical technique to avoid the use of FFT is presented. Also, a formula for estimating the discretization error is given.>

A method for computing the moments of a nonuniformly distributed RLGC element is presented. A recursive formula for the evaluation of moments of hybrid parameters, characterizing the distributed element, is derived from the spectral method solution of a system of ordinary differential equations.>

The crosstalk in a system containing n(n>or=2) lossless microstrip transmission lines is formulated as a linear function in time. The maximum crosstalk is computed by evaluating the crosstalk at certain breakpoints in time. The technique also provides the pattern (rising or falling) of input voltages and their relative delays for which the maximum crosstalk occurs. This pattern is usually determined by the system parameters. Since the maximum crosstalk determines the faulty vs fault-free operation, the pattern found could be used for testing integrated logic circuits during the design stage.>