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Pankaj Mayor

dblp:42/4940 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1991
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 75% Performance modeling and evaluation · 25%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware simulation
compiled simulation		 0.011991
A System for Fault Diagnosis and Simulation of VHDL Descriptions · DAC 1991
Electronic design automation › hardware verification and test
fault diagnosis		 0.011991
A System for Fault Diagnosis and Simulation of VHDL Descriptions · DAC 1991
Electronic design automation
hardware verification and test		 0.011991
A System for Fault Diagnosis and Simulation of VHDL Descriptions · DAC 1991
Performance modeling and evaluation
simulation		 0.011991
A System for Fault Diagnosis and Simulation of VHDL Descriptions · DAC 1991

Methods — techniques the papers use, named apart from their topics

stuck-at fault model · 0.0discrete-event simulation · 0.0constraint suspension · 0.0
YearPublicationVenuePosition
1991 A System for Fault Diagnosis and Simulation of VHDL Descriptions
abstract
This paper describes a compiler and algorithms for simulation and fault diagnosis of computer hardware modeled in VHSIC Hardware Description Language(VHDL).Given a VHDL description, the compiler creates an internal representation.For simulation, a discrete-event based compiled code simulation algorithm is used.For fault diagnosis, a hierarchical approach using the stuck-at fault model at the first level and the arbitrary failure model at the second level, is used.The diagnosis algorithm reasons from first principles using constraint suspension.
Vijay Pitchumani, Pankaj Mayor, Nimish Radia
 DAC2
1991 Fault Diagnosis using Functional Fault Models for VHDL descriptions
abstract
This paper describes algorithms for fault diagnosis of computer hardware modeled in VHDL [1,2,3,4]. Given a VHDL description, the compiler creates an internal representation. For fault diagnosis, a hierarchical approach using the stuck-at fault model at the first level and the arbitrary failure model at the second level, is used. The diagnosis algorithm reasons from first principles using constraint suspension.
Vijay Pitchumani, Pankaj Mayor, Nimish Radia
 ITC2