Two 1 novel automatic generation methods for analog layout—a symmetrical twin-row method for MOS transistors and a twisted common-centroid method for capacitor arrays—are introduced. Based on the proposed layout styles and the corresponding algorithms, the symmetry and common-centroid placement patterns for analog devices are realized to guarantee matching properties. On this basis, as the most prominent contribution of this article, channel routing-based algorithms for the proposed layout styles are presented and could achieve 100% routability due to well-arranged devices and corresponding low routing complexity. The algorithms benefits include a small layout area that maximizes the diffusion-sharing of MOS transistors and less routing layer usage for common-centroid device arrays. Moreover, we successfully applied our algorithms to the layout designs of two typical analog modules including a two-stage operating amplifier and a Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). The generated layouts and the circuit simulation results demonstrate the effectiveness of our algorithms in terms of their routability and matching properties. Our algorithms can also be extended to apply to a variety of essential MOS analog circuits.

This paper presents a low supply voltage design of stochastic flash ADC, introducing an inverter-based comparative unit which is used as the front-end. A stochastic flash ADC has a significant advantage in reducing the supply voltage, while it needs a large number of comparators even for middle-level resolution. A key of our design is in the simplicity of the structure, and it enables us to decrease the number of transistors by replacing a comparator with a chain of inverters. Plus, the supply voltage can go down to 0.6V on 65nm process, as well as it can be designed with fully digital standard cells. We introduce a latch circuit combining with the chain of inverters for the signal stability, and discuss about an appropriate circuit structure for the resolution by analyzing three different structures. In the simulation, we demonstrate fundamental but promising results for a low voltage ADC design.

The CAD Contest at ICCAD[1], [2], [3], [4], [5], [6] is a challenging, multi-month R&D competition, focusing on modern and practical problems at the forefront of Electronic Design Automation (EDA). In its sixth year, the 2017 CAD Contest at ICCAD is among the premier worldwide academic programming contests, attracting 122 teams from 10 different regions/countries. This year, three contest problems in the areas of ECO logic synthesis, ECO routing and placement legalization for the advanced nodes are called for competition. We hope that the contest evaluation frameworks and benchmarks boost research on these critical problems and help EDA community discover novel, efficient, high-quality solutions to advance the state-of-the-art in EDA.

The CAD Contest at ICCAD is a challenging, multi-month competition, focusing on advanced, real-world problems in the field of Electronic Design Automation (EDA). In its fifth year, the 2016 CAD Contest at ICCAD attracted 135 teams from 11 regions/countries. Three critical EDA problems, in the areas of design verification, logic synthesis, and design for manufacturing (DFM), were called for competition this year. We hope that the contest benchmark suites and evaluation infrastructure boost research in the related areas and help EDA community find novel and high-quality solutions to the problems.

In the MOS analog layout, variability suppression is becoming a major issue, as is layout efficiency. Introducing a transistor array (TA) style to analog layout, this article addresses the layout-dependent variability based on the measurement results of test chips on 90nm CMOS process. In TA style, a large transistor is decomposed into a set of unified subtransistors, which are connected in series or parallel. Focusing on one row layout of diffusion sharing for the multiple gates, we analyze the current direction-dependent variability and the leakage current via off-gates for the electrical isolation. Furthermore, we present several analog design cases on TA including analysis of the impact on the DC characteristics caused by the transistor channel decomposition.

This paper presents a layout-dependent manufacturability for analog integrated circuits. We focus on the relative variability of input op-amp-pair used in an instrumentation amplifier (in-amp). We propose a subblock-level matching layout style such that subblocks of the op-amp-pair are superimposed aiming to suppress the relative variability dependent on the layout. We fabricate chips according to five superposed layout styles and evaluate the relative variability in terms of the DC offset, so that we demonstrate the most effective layout style. Besides, we provide a manufacturability simulation methodology to evaluate the in-amp considering the relative variability of the op-amp-pair based on the measurement results. Comparing the simulation result and the performances of fabricated in-amps, we are convinced our methodology can evaluate the layout-dependency of the manufacturability by the simulation.

This paper presents an energy efficient algorithm for 1.2V 9- bit 50MSps Successive Approximation Register (SAR) ADC. This conversion mechanism is based on pre-charge VCM and achieves the twice of the input signal range beyond the supply voltage. Besides, this algorithm requires (i)a dynamic comparator with dual outputs and (ii)an additional comparison stage before each redistribution stage in the preconversion. We can reduce the switching power over 10% when compared to the merged capacitor switching (MCS) method with double input range of supply voltage. We design the SAR ADC following our idea on 65nm CMOS technology. The simulation results show 2.5dB better signal- to-noise-and-distortion ratio (SNDR) than the conversion method. Our ADC consumes a total energy of 0.504 mW at a 1.2V supply and 50MSps.

No abstract available.

In nano-scale process, shallow trench isolation (STI) stress and well proximity effect (WPE) affect the threshold voltage of MOSFET as well as the performance of the system-on-chips (SoC). As one of the most sensitive and highest density circuit, SRAMs must be designed considering the stress effect analysis. The variation of the stress effect causes dramatical change of the threshold voltage especially beyond 90nm process. In this paper, we present an SRAM macro design methodology dealing with a significant trade-off among area, leakage power and delay by introducing non-uniform parameterized SRAM cells. Experimental results show that this technique can reduce the leakage power and macro area of a 32×64 SRAM by 12.5% and 18.2% respectively.

In retargeting of a nano-watt CMOS reference circuit, we adopt an advanced compact MOSFET model to describe the drain current consistently in strong and weak inversion levels. Based on this model, we describe all bias conditions in terms of ratios of the channel widths and lengths. Taking the effect of very long channels into account, we formulate the threshold voltage as a function of the drain-source voltage. Furthermore, we introduce a tuning parameter with the empirical range and fix all transistor sizes sweeping this parameter as well as applying a simulation. In case studies, we retargeted a circuit from the 180nm/1.8V process to the 90nm/1.2V, 2.5V, 3.3V processes. Besides, we fabricated the circuit in the 90nm/1.2V process, and confirmed the good measurement results such as less than 12.8%/V supply voltage variation and only 1.1nW power consumption.

This paper presents a novel way to analyze the variation of analog circuits taking layout-dependent variation parameters into consideration. Focusing on 90nm process, we reveal Monte Carlo simulation based on independent parameters Vth and ² collected from the test chip can not account for the measurement results of fabricated op-amp circuits with different layouts styles. In the comparison of the simulation and the measurement results, we clarify the impacts by the parasitics of wires and STI stress as well as the correlation of the variation of Vth and ². Besides, we also propose an efficient approach of Monte Carlo simulation converting all variation parameters to the channel widths of MOSFETs.

For analog circuits, the current source is one of the most essential functions, and variation of its characteristic seriously influences to the accuracy of the performance. This paper presents a new methodology for analyzing the layout dependency of the variation of the current source transistor. We employ a current-driven D-A converter to investigate the dependency of the current source upon the relative accuracy and the ¿. We implemented the D-A converts with various layout structures into TEG(Test Element Group), and evaluated them. The analysis convinced us that the diffusion sharing and gate folding significantly influence to the variation of ¿ and relative accuracy.

This paper presents a novel regularity evaluation of placement structure and MOS analog specific layout techniques called diffusion sharing and well island generation, which are developed based on sequence-pair. The regular structures such as topological row, array and repetitive structure are characterized by the way of forming subsequences of a sequence-pair. A placement objective is formulated balancing the regularity and the area efficiency. Furthermore, diffusion sharing and well island can be also identified looking into forming of a sequence-pair. In experiments, we applied our regularity-oriented placement mixed with the constrait-driven technique to real analog designs, and attained the results comparable to manual designs even when imposing symmetry constraints. Besides, the results also revealed the regularity serves to increase row-structures applicable to the diffusion-sharing for the area and wire-length saving.

This paper addresses the problem of transistor decomposition, which can be used in high accuracy analog applications and structured analog design. We made a test chip to verify the feasibility of the transistor decomposition because of the lack of theoretical support. The DC/AC measurement results from the chip suggests that the decomposition, the transistor channel tuning, as well as structured analog design based on the transistor array are applicable. Also our test chip shows that design with transistor array can suppress the variation of Vthstemmed from CMP process. Based on this conclusion, we propose a simple framework with transistor array for structured analog layout generation, which involves the transistor decomposition. Using this framework, we generate several layouts for a typical CMOS OPAMP circuit and compare the automatically generated layouts with the manual layouts. Although the layout sizes of the transistor array based OPAMPs are slightly bigger than that of the manual designs, the automatic layout generation is much faster than manually synthesizing the layout.

Size of STI wells is another significant factor to affect the stress magnitude (device mobility) besides size of transistor active regions. In this paper, we present a technique for improving device mobility in the critical path via global STI well width adjusting following the chip placement stage. The methodology formulates the original device mobility enhancement problem as a series of convex geometric programs(GP), which is based on two observations that: (1)Minimum layout perturbation objective could be reached when introducing into an iterative GP approximation procedure; (2)Terms in charge of PMOS channel mobility optimization could be modeled as posynomials of design variables, that is, the width of STI wells. Finally, by applying the presented technique to several IBM-PLACE benchmarks, and solving the resulted GP problems by a GP solver named MOSEK, we are able to demonstrate its effectiveness.

This paper presents an efficient algorithm for incremental buffer insertion and module resizing for a full-placed floorplan. Our algorithm offers a method to use the white space in a given floorplan to resize modules and insert buffers, and at the same time keep the resultant floorplan as close to the original one as possible. Both the buffer insertion and module resizing are modelled as geometric programming problems, and can be solved extremely efficiently using new developed solution methods. The experimental results suggest that the the wirelength difference between the initial floorplan and result is quite small (less than 5%), and the global structure of the initial floorplan is preserved very well.

Shallow trench isolation(STI) is the mainstream CMOS isolation technology for advanced integrated circuits. While STI process gives the isolation benefits due to its scalable characteristics, exploiting the compressive stress exerted by STI wells on device active regions to improve performance of devices has been one of the major industry focuses. However, in the present research of VLSI physical design, there has no yet a global optimization methodology on the whole chip layout to control the size of the STI wells, which affects the stress magnitude along with the size of active region of transistors. In this paper, we present a novel methodology that is capable of determining globally the optimal STI well width following the chip placement stage. The methodology is based on the observation that both of the terms in charge of chip width minimization and transistor channel mobility optimization in the objective function can be modeled as posynomials of the design variables, that is, the width of STI wells. Then, this stress aware placement optimization problem could be solved efficiently as a convex geometric programming (GP) problem. Finally, by a MOSEK GP problem solver, we do our STI width aware placement optimization on the given placements of some GSRC and IBM-PLACE benchmarks. Experiment results demonstrated that our methodology can obtain decent results with an acceptable runtime when satisfy the necessary location constraints from DRC specifications.

In analog circuits, blocks need to be placed symmetrically to satisfy the devices matching. Different from the existing constraint-driven approaches, the proposed topological symmetry structure enables us to generate a symmetrical placement without any constraint. Simulated annealing is utilized as the framework of the optimization, and we propose new move operation to maintain the placement's topological symmetry. By inserting dummy blocks, we present a physical skewed symmetry structure allowing non-symmetry partly, so that to enhance the placement on area and wire length. Besides, we incorporate regularity into the evaluation of placement. Experiments shows that our approach generated topological complete symmetry placements without much compromise on chip area and wire length, compared to the placements with no symmetry.

This paper aims at developing a transistor-level programmable technology which is composed of two key mechanisms; One is that a MOS transistor is divided into sub-transistors connected in parallel, so that the transistor behaves various characteristics by switching the parallel connection. The other mechanism changes Vthand gmof the transistor by adjusting the bulk potential based on body effect. These mechanisms are combined and embedded into an opamp circuit. In the post-layout simulation, the results showed our mechanisms could tune the circuit performance such as the gain continuously as well as over a wide range.

This paper introduces a new concept of floorplanning and block placement, called structured placement. Regularity is a key criterion of structured placement so that placement can make progress beyond constraint-driven approaches. This paper formulates the topological regularity that is extractable from a sequence-pair. Regular structures like arrays and rows are defined on a single-sequence that is a kind of standard representation of a sequence-pair. We extract regular structures from a single-sequence in 0(n), and then evaluate the structures by quantifying the regularity as an objective function. Besides, we propose a new simulated annealing (SA) framework, called dual SA, where we convey a constructive feature to an SA framework, so that it attains a placement balancing the size of regular structures against the area efficiency. In experiments, we apply our structured placement to analog block designs, and reveal the definite advantage that our placements contain many regular structures such as rows and arrays without increasing the chip area and the wire length, compared to the existing placement.

Given a set of placed blocks, we present an algorithm that minimally spaces the blocks to ensure routability under several assumptions. By performing a binary search on total width/height of the chip and optimal routing area can be obtained. The proposed technique utilizes a piecewise linear model of the channel width. Based on this model, we introduce LP formulation to determine the optimal channel width considering pin alignment by balancing the wire length and the channel width.

The shape-based routing needs a routing architecture with a geometrical computation framework on it. This paper introduces a novel routing architecture, Oct-Touched Tile (OTT), with a geometrical computation method along the horizontal- and vertical-constraints. The architecture is represented by the tiles spreading over the 2-D plane. Each tile is flexible to satisfy the constraints imposed for non-overlapping and sizing request. In this framework, any practically useful path finding and shape-based sizing technique are executed on the same architecture. Our system ex-perimentally demonstrates the performance comparable to a commercial tool.

A challenge to an automated layout of analog IC starts with the insight into a high quality placement crafted by experts. It has been observed that such a placement comprises clusters corresponding to groups of matched devices and devices are placed faithfully to the drawn schema while the placement is still compacted. This paper proposes a novel device-level placement based on Sequence-Pair which includes an effective representation of clusters extracted from the schema. A key idea is to capture a topological structure of clusters in order to place clusters at as faithful positions to those in the schema. We represent this structure in terms of ABLR-relations which can be translated into Sequence-Pair. In experiments, we tested our algorithm for industrial instances and compared the results with those by manual. We showed that our results were better than manual results by, on average, 12.8% and 18.1% with respect to area and net-length.

Sequence-pair-based floorplanning has revealed the limit of its usefulness in very large scale integration layout design, the key issue being that it is nonhierarchical and indifferent to the preceding step of partitioning. This paper restructures the sequence pair enhanced to a pair of logic expressions to accept the constraint induced by the previous step - the balanced bipartition. Since the bipartition is hierarchical in nature, the transferred constraint is called the hierarchical superconstraint. Since floorplanning based on this data structure automatically works cooperatively with the partitioning, it is called the consistent floorplanning, which has potential to store all the feasible floorplans under the constraint induced by any balanced binary search. As a typical example, we focus on clock-tree synthesis by H-tree. Experiments are given to show better achievements in length and wire density for module-based circuits and clock trees.

Sequence-Pair based floorplanning has been revealed its limit of usefulness in VLSI physical design. Among reasons, the key issue is in its being non-hierarchical and indifferent to the preceding step of partitioning. This paper restructure the algorithm by the idea that the partition algorithm produces the constraint that is imposed on the sequence-pair data. The partition algorithm is the one based on the balanced-bipartition that works hierarchically. Thus a new floorplan algorithm that is consistent with the hierarchical partition algorithm is constructed. This is enhanced to include other algorithms that are based on the binary search. Here, a clock-tree synthesis by H-tree is shown to be consistent. Experiments are given to show better achievements in length and wire-density.

Abstract | Given a route which connects terminal-s on a one-layer routing area(Steiner tree), \n ip is a procedure that makes a current route change its con-guration within its peripheral domain. A \nip reforms a route by replacing one of its edges with a minimal detour. A route can \nip one nearby obstacle. If the obstacle is another route, a more organized operation, called the dual \nip, is applied to a pair of routes. The idea is enhanced to the 2-layer hv-routing. The per-formance of \nip and dual \nip was experimented in simulated annealing which reforms a route or a set of routes with respect to the evaluation function of mul-tiple objectives. Some unique and satisable results were observed. I.

A main task in designing IC/PCB is to pack rectilinear modules under various constraints and objectives. If modules are all rectangles without any positional constraint, recently proposed BSG and Sequence-pair based packing algorithms have been proved to work fast enough for practical use. Focusing BSC, to support an effective use, this paper develops techniques to handle rectilinear modules and modules with positional constraints. First a solution is proposed for pre-placed modules. It is to give a linear order to the floating modules following which they are embedded in packing. In the course, the pre-placed modules are considered as the constraints such that no floating modules are forbidden to be placed. The packing of modules including rectilinear ones is solved by applying the above techniques after rectilinear modules are sliced into a set of rectangles. Experimental results on industrial PCB-data showed that the proposed algorithm outputs high quality packings.

Article The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications Share on Authors: Shigetoshi Nakatake Department of Electrical and Electronic Engineering, Tokyo Institute of Technology Department of Electrical and Electronic Engineering, Tokyo Institute of TechnologyView Profile , Keishi Sakanushi Department of Electrical and Electronic Engineering, Tokyo Institute of Technology Department of Electrical and Electronic Engineering, Tokyo Institute of TechnologyView Profile , Yoji Kajitani Department of Electrical and Electronic Engineering, Tokyo Institute of Technology Department of Electrical and Electronic Engineering, Tokyo Institute of TechnologyView Profile , Masahiro Kawakita Semiconductor Systems Engineering Center, Toshiba Corporation Semiconductor Systems Engineering Center, Toshiba CorporationView Profile Authors Info & Claims ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided designNovember 1998 Pages 418–425https://doi.org/10.1145/288548.289064Online:01 November 1998Publication History 9citation195DownloadsMetricsTotal Citations9Total Downloads195Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

A floorplannar that can handle convex-rectilinear blocks is developed by enhancing the BSG-based packing algorithm.The ideas are in the intr~ duction of (1) multi-rectangle representation of a block as a superpose of element-rectangles, (2) parametric-BSG as a generalization of the BSG, (3) mult i-BSG which is an arrangement of plural BSG's on a multi-layer, and (4) layer sharing condition of element-rectangles so that non-overlapping is di~ cussed on each layer.A solution space of packings is defined as the set of packings generated by changing parametric-BSG and room assignments.It is guaranteed to contain an optimal packing if the BSG is not smaller than a certain size.A floorplan based on a simulated annealing w= implemented.In experiments, it output highly compressed packings.

A new method of packing the rectangles is proposed with applications to integrated circuit (IC) layout design. A special work-sheet, called the bounded-sliceline grid, is introduced. It consists of special segments that dissect the plane into rooms to which binary relations "right-of" and "above" are associated such that any two rooms are uniquely in either relation. A packing is obtained through an assignment of the modules into the rooms followed by a compaction procedure. Changing the assignments by swapping the contents of two rooms, a simulated annealing strategy is implemented to search for a good packing. Empirical results show that hundreds of rectangles are packed with a quite good quality in area efficiency. A wide adaptability is demonstrated specific to IC layout design. Ideas to handle a multilayer, nonrectangular chips with L-shaped modules are suggested.

A new method of packing rectangles (modules) is presented with applications to IC layout design. It is based on the bounded-sliceline grid (BSG) structure. The BSG dissects the plane into rooms associated with binary relations "right-to"and "above" such that any two rooms are uniquely in either relation. A packing is obtained through an assignment of modules on the BSG. Followed by physical realization BSG-PACK. A simulated annealing searches for a goon packing of all packings by changing the assignments. Experiments showed that hundreds of rectangles are easily packed in a small rectangle area (chip) with quite good quality in area efficiency. A wide adaptability is demonstrated specific to IC layout design. Remarkable examples are: the chip is not necessarily rectangle, L-shaped modules and modules which are allowed to partially overlap each other can be handled.

The earliest and the most critical stage in VLSI layout design is the placement. The background is the rectangle packing problem: given a set of rectangular modules of arbitrary sizes, place them without overlap on a plane within a rectangle of minimum area. Since the variety of the packing is uncountably infinite, the key issue for successful optimization is the introduction of a finite solution space which includes an optimal solution. This paper proposes such a solution space where each packing is represented by a pair of module name sequences, called a sequence-pair. Searching this space by simulated annealing, hundreds of modules have been packed efficiently as demonstrated. For applications to VLSI layout, we attack the biggest MCNC benchmark ami49 with a conventional wiring area estimation method, and obtain a highly promising placement.

The first and the most critical stage in VLSI layout design is the placement, the background of which is the rectangle packing problem: Given many rectangular modules of arbitrary site, place them without overlapping on a layer in the smallest bounding rectangle. Since the variety of the packing is infinite (two-dimensionally continuous) many, the key issue for successful optimization is in the introduction of a P-admissible solution space, which is a finite set of solutions at least one of which is optimal. This paper proposes such a solution space where each packing is represented by a pair of module name sequences. Searching this space by simulated annealing, hundreds of modules could be successfully packed as demonstrated. Combining a conventional wiring method, the biggest MCNC benchmark ami49 is challenged.