DB2 with BLU Acceleration deeply integrates innovative new techniques for defining and processing column-organized tables that speed read-mostly Business Intelligence queries by 10 to 50 times and improve compression by 3 to 10 times, compared to traditional row-organized tables, without the complexity of defining indexes or materialized views on those tables. But DB2 BLU is much more than just a column store. Exploiting frequency-based dictionary compression and main-memory query processing technology from the Blink project at IBM Research - Almaden, DB2 BLU performs most SQL operations - predicate application (even range predicates and IN-lists), joins, and grouping - on the compressed values, which can be packed bit-aligned so densely that multiple values fit in a register and can be processed simultaneously via SIMD (single-instruction, multipledata) instructions. Designed and built from the ground up to exploit modern multi-core processors, DB2 BLU's hardware-conscious algorithms are carefully engineered to maximize parallelism by using novel data structures that need little latching, and to minimize data-cache and instruction-cache misses. Though DB2 BLU is optimized for in-memory processing, database size is not limited by the size of main memory. Fine-grained synopses, late materialization, and a new probabilistic buffer pool protocol for scans minimize disk I/Os, while aggressive prefetching reduces I/O stalls. Full integration with DB2 ensures that DB2 with BLU Acceleration benefits from the full functionality and robust utilities of a mature product, while still enjoying order-of-magnitude performance gains from revolutionary technology without even having to change the SQL, and can mix column-organized and row-organized tables in the same tablespace and even within the same query.

An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-flops into scan chains, which determines how many chains can be deactivated per pattern.

Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can be used for reducing the power consumption during test. Here, we present an efficient algorithm for the automated generation of a test plan that keeps fault coverage as well as test time, while significantly reducing the amount of wasted energy. A fault isolation table, which is usually used for diagnosis and debug, is employed to accurately determine scan chains that can be disabled. The algorithm was successfully applied to large industrial circuits and identifies a very large amount of excess pattern shift activity.

Built-in self test is a major part of the manufacturing test procedure for the cell processor. However, pseudo random patterns cause a high switching activity which is not effectively reduced by standard low power design techniques. If special care is not taken, the scan-speed may have to be reduced significantly, thus extending test time and costs. In this paper, we describe a test power reduction method for logic BIST which uses test scheduling, planning and scan-gating. In LBIST, effective patterns that detect additional faults are very scarce after a few dozens of scan cycles and often less than one pattern in a hundred detects new faults. In most cases, such an effective pattern requires only a reduced set of the available scan chains to detect the fault and all don't-care scan chains can be disabled, therefore significantly reducing test power

In this paper a novel hierarchical DfT methodology is presented which is targeted to improve the delay fault testability for external testing and scan based BIST. After the partitioning of the design into high frequency macros, the analysis for delay fault testability already starts in parallel with the implementation at the macro level. A specification is generated for each macro that defines the delay fault testing characteristics at the macro boundaries. This specification is used to analyse and improve the delay fault testability by improving the scan chain ordering at macro-level before the macros are connected together into the total chip network. The hierarchical methodology has been evaluated with the instruction window buffer core of an out-of-order processor. It was shown that for this design practically no extra hardware is required.

In this paper an approach is presented for thehierarchical verification of the memory control units, I/O adaptersand processor interconnect units as found in multiprocessorcomputer systems. It is shown how such units could be verifiedbetter and faster by the introduction of random executable timingdiagrams and associated CAD tool support. Furthermore, itis shown how the timing diagrams for the unit network verificationare easily derived from the timing diagrams specified for theunits. The multiprocessor hardware test showed the effectivenessof the proposed verification approach.

In this paper a novel hierarchical test program development approach is presented for scan testable circuits. We will show how the test program for scan designs can be developed incrementally, in-line with the hierarchical construction ofthesystem netlist, by differentiating between interior and exlerior tests for each model. Furthermore, it will be shown that byintroducing test assembly, such an hierarchical test program development approach is also applicable when nwcros requiring dedicated test procedures are in use. Therefore itprovides an attractive enhancement of the Macro Testing technique.

A novel incremental procedure for the hierarchical assembly of macro test specifications into a chip test program is presented. To solve test generation/application problems, a bottom-up symbolic test assembly procedure that proceeds in line with the construction of the system is proposed. It is shown that for a modular design approach, this procedure can be extended with design-for-testability features to ensure that all macro tests are assembled into a chip test program. The approach is exemplified by the design of a decimation filter for a Sigma / Delta A/D (analog-to-digital) converter.>

Test concepts for artificial neural networks are discussed. It is shown that the traditional design-for-test techniques such as (boundary) scan are of limited use owing to the high connectivity and redundancy of neural networks. An information-theoretical approach that allows for wafer as well as chip test is outlined. This approach involves testing directly on the macro properties of the neural network. The influence of device faults and built-in fault tolerance of the network is captured in so-called fault tolerant curves. These curves, obtained by simulation, link the various macro and micro properties together and allow an information-driven test of the neural network.>

The design of synchronously testable asynchronous macros is investigated. A novel implementation model which uses an explicit state register is presented. This approach makes it possible to apply scan and boundary tests to nonsynchronous VLSI systems. The state register is composed of SR (set-reset) flip-flops, which can operate in asynchronous, synchronous, and (token) scan mode. It is shown that these controllers are synchronously testable and can be derived directly from a control graph description. The approach is exemplified by the design and test of a self-timed ALU (arithmetic and logic unit).>