Commercial FPGAs from major vendors are extensively optimized, and fabrics use many hand-crafted custom cells, including switch matrix multiplexers and configuration memory cells. The physical design optimizations commonly improve area, latency (=speed), and power consumption together. This paper is dedicated to improving the physical implementation of FPGA tiles and the configuration storage in SRAM FPGAs. This paper proposes to remap configuration bits and interface wires to implement tightly packed tiles. Using the FABulous FPGA framework, we show that our optimizations are virtually for free but can save over 20% in area and improve latency at the same time. We will evaluate our approach in different scenarios by changing the available metal layers or the requested channel capacity. Our optimizations consider all tiles and we propose a flow that resolves dependencies between the CLBs and other tiles. Moreover, we will show that frame-based reconfiguration is, in almost all cases, better than shift register configuration.

At the end of CMOS-scaling, the role of architecture design is increasingly gaining importance. Supporting this trend, customizable embedded FPGAs are an ingredient in ASIC architectures to provide the advantages of reconfigurable hardware exactly where and how it is most beneficial. To enable this, we are introducing the FABulous embedded open-source FPGA framework. FABulous is designed to fulfill the objectives of ease of use, maximum portability to different process nodes, good control for customization, and delivering good area, power, and performance characteristics of the generated FPGA fabrics. The framework provides templates for logic, arithmetic, memory, and I/O blocks that can be easily stitched together, whilst enabling users to add their own fully customized blocks and primitives. The FABulous ecosystem generates the embedded FPGA fabric for chip fabrication, integrates Yosys, ABC, VPR and nextpnr as FPGA CAD tools, deals with the bitstream generation and after fabrication tests. Additionally, we provide an emulation path for system development. FABulous was demonstrated for an ASIC integrating a RISC-V core with an embedded FPGA fabric for custom instruction set extensions using a TSMC 180nm process and an open-source 45nm process node.

This demonstration shows the steps a designer has to take to specify and implement a chip with an embedded FPGA (eFPGA) using the FABulous open-source toolchain. We also show how the architecture graph is automatically generated for the open-source FPGA CAD tools (Yosys, ABC, nextpnr) to compile Verilog all the way to a bitstream. Ultimately, we demonstrate such bitstreams running on our FlexBex chip, which integrates an Ibex RISC-V core from lowRISC together with a FABulous eFPGA. The system supports multiple partially reconfigurable regions for hosting reconfigurable instruction set extensions, and the fabric provides logic, DSP, and memory slices.

Both asynchronous and reconfigurable techniques are likely to become increasingly important in the future due to greater device unreliability and variability at nano-scale dimensions. One promising asynchronous technique, Null Convention Logic (NCL) is a symbolically complete quasi-delay insensitive logic system that is inherently self-determined, locally autonomous and self-synchronizing. As current FPGA devices are set up for clocked synchronous logic they are not well suited to reconfigurable asynchronous systems. A reconfigurable block supporting NCL that is intended to form one component of a FPGA organization is proposed and analyzed. Both single-rail and dual-rail LUTs are described. The block design and layout is described and analyzed using an advanced 45nm bulk CMOS fabrication process.