Despite significant advancements in deep classification techniques and in-lab automatic optical inspection (AOI) models for long-tailed or highly imbalanced data, applying these approaches to real-world IC defect classification tasks remains challenging. This difficulty stems from two primary factors. First, real-world conditions, such as the high yield-rate requirements in the IC industry, result in data distributions that are far more skewed than those found in general public imbalanced datasets. Consequently, classifiers designed for open imbalanced datasets often fail to perform effectively in real-world scenarios. Second, real-world samples exhibit a mix of class-specific attributes (e.g., defect types) and class-agnostic, domain-related features (e.g., design characteristics of product lines). This complexity adds significant difficulty to the classification process, particularly for highly imbalanced datasets. To address these challenges, this paper introduces the IC-Defect-14 dataset, a large, highly imbalanced IC defect image dataset sourced from AOI systems deployed in real-world IC production lines. This dataset is characterized by its unique “intra-class clusters” property, which presents two major challenges: large intra-class diversity and high inter-class similarity. These characteristics, rarely found simultaneously in existing public datasets, significantly degrade the performance of current state-of-the-art classifiers for highly imbalanced data. To tackle this challenge, we propose the Regional Channel Attention-based Multi-Expert Network (ReCAME-Net). This network follows a multi-expert classifier framework and integrates a regional channel attention module, metric learning losses, a hard category mining strategy, and a knowledge distillation procedure. Extensive experimental evaluations demonstrate that ReCAME-Net outperforms previous state-of-the-art models on the IC-Defect-14 dataset while maintaining comparable performance and competitiveness on general public datasets. Our resources can be found at https://github.com/YoursEver/ReCAME-Net.

Recent advances in VLSI fabrication technology have led to die shrinkage and increased layout density, creating an urgent demand for advanced hotspot detection techniques. However, by taking an object detection network as the backbone, recent learning-based hotspot detectors learn to recognize only the problematic layout patterns in the training data. This fact makes these hotspot detectors difficult to generalize to real-world scenarios. We propose a novel lithography simulator-powered hotspot detection framework to overcome this difficulty. Our framework integrates a lithography simulator with an object detection backbone, merging the extracted latent features from both the simulator and the object detector via well-designed cross-attention blocks. Consequently, the proposed framework can be used to detect potential hotspot regions based on 1) the variation of possible circuit shape deformation estimated by the lithography simulator and 2) the problematic layout patterns already known. To this end, we utilize RetinaNet with a feature pyramid network as the object detection backbone and leverage LithoNet as the lithography simulator. Extensive experiments demonstrate that our proposed simulator-guided hotspot detection framework outperforms the previous state-of-the-art methods on real-world data.

In this paper, we proposed a fine-grained attribute pre-labeling method based on the multi-label recovery techniques. Given a fine-grained image dataset with overlooked attributes in its annotation vectors, our method can predict those missing attribute labels by learning the between-label dependency based on the estimated similarity between known attributes and the similarity of extracted deep image features. Furthermore, to prevent the learnable label dependency matrix from converging to a trivial solution, we designed a trace-loss to penalize the self-dependency of attributes. Comprehensive experiments on the CUB-200-2011 dataset show that, given a training set with 40% of attribute labels randomly dropped: i) our approach achieves a pre-labeling performance with an mAP value of 30.7 on a blind testing set, and ii) the missing attributes in the training set can be corrected with an accuracy of 89%. Our method can effectively and robustly perform the fine-grained pre-labeling task.

Memory-centric designs deploy computation to storage and enable efficient in-memory computation while avoiding massive amount of data movement. The in-memory-computing schemes have shown distinct advantages and concerns when applying to different types of memory technologies, from conventional SRAM, DRAM to emerging ReRAM. Moreover, the next-generation smart edge systems are expected to support various intelligent applications by employing multi-task machine learning models which would be dynamically activated. To attain an efficient design within short design cycle, it is imperative to have an integrated design framework with automated tools to support hybrid memory systems and perform effective optimization across design stages. This work will introduce a unified framework which integrates EDA solutions to address the design and optimization challenges at different aspects of next-generation memory-centric designs, including fast reconfiguring in-memory/near-memory computing designs to provide optimized solutions (behavioral models and APR cell layouts) for designers to choose the best suitable architectures for their applications.

Executing functional components in pipeline on heterogeneous multi-core platforms can greatly improve the parallelism but require great amount of data communication among processes and threads. Our studies showed that existing inter-process/thread communication protocols consist of many unnecessary memory copies and prolong the execution of the applications on heterogeneous multi-core platforms. NTU ICPC uses polling-base mail notification to unnecessary context switches, and designs a memory subsystem to manage the input and output data between the senders and receivers. The protocol was implemented and evaluated on heterogeneous multi-core platform for several use scenario including H.264 encoding process. The evaluation results show that the communication overhead on sender side is independent of the data size and that on receiver side is greatly shortened, compared to several inter-process Communication (IPC) protocols including mailbox, message queue, and shared memory. When encoding H.264 video clips, the encoding frame rates increase for more than 30%. Our experiments also showed that the communication overhead accounts 40% to 50% of total execution time in average for H.264 video decoding applications. In this paper, we present the design and implementation of zero-buffer inter-core process communication protocol, named NTU ICPC, to shorten communication overhead for pipeline executed applications on heterogeneous multi-core platforms.