Demo Data from EDBT 2026 / reviewers in the wild / expert
Mahmoud Said
dblp:42/7846
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 2011
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Memory systems · 59% Parallel and multicore computing · 23% Hardware reliability and fault tolerance · 18% | |
| Software engineering, system software, and programming languages
1 paper |
Software testing · 50% Concurrent programming · 50% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Concurrent programming
concurrency bugs |
0.1 | 1 | 2011 | Coverage guided systematic concurrency testing · ICSE 2011 |
Software testing
concurrency testing |
0.1 | 1 | 2011 | Coverage guided systematic concurrency testing · ICSE 2011 |
Parallel and multicore computing › parallel computing › parallel program debugging
deterministic replay |
0.1 | 1 | 2011 | Offline symbolic analysis to infer Total Store Order · HPCA 2011 |
Memory systems › memory consistency
memory consistency model |
0.1 | 1 | 2011 | Offline symbolic analysis to infer Total Store Order · HPCA 2011 |
Memory systems › memory consistency › memory consistency model
total store order |
0.1 | 1 | 2011 | Offline symbolic analysis to infer Total Store Order · HPCA 2011 |
Hardware reliability and fault tolerance
execution replay |
0.1 | 1 | 2009 | Offline symbolic analysis for multi-processor execution replay · MICRO 2009 |
Memory systems
cache coherence |
0.1 | 2 | 2011 | Offline symbolic analysis to infer Total Store Order · HPCA 2011 Offline symbolic analysis for multi-processor execution replay · MICRO 2009 |
Methods — techniques the papers use, named apart from their topics
systematic testing · 0.1satisfiability modulo theories · 0.1offline symbolic analysis · 0.1dynamic analysis · 0.1coverage-guided testing · 0.1symbolic analysis · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2011 | Offline symbolic analysis to infer Total Store OrderabstractAbility to record and replay an execution can significantly help programmers debug their programs, especially parallel programs. De-terministically replaying a multiprocessor's execution under a relaxed memory model has remained a challenging problem. This is an important problem as most modern processors only support a relaxed memory model to enable many performance critical optimizations. The most common consistency model implemented in processors is the Total Store Order (TSO). We present an efficient and low-complexity processor based solution for recording and replaying under the Total Store Order (TSO) memory model. Processor provides support for logging data fetched on cache misses. Using this information each thread can be de-terministically replayed. A TSO-compliant casual order between the shared-memory accesses executed in different threads is then inferred using an offline algorithm based on Satisfiability Modulo Theory (SMT) solver. We also discuss methods to bound the search space during offline analysis and several optimizations to reduce the offline analysis time. Mahmoud Said, Satish Narayanasamy, Zijiang Yang 0006 |
HPCA | 2 |
| 2011 | Coverage guided systematic concurrency testingabstractShared-memory multi-threaded programs are notoriously difficult to test, and because of the often astronomically large number of thread schedules, testing all possible interleavings is practically infeasible. In this paper we propose a coverage-guided systematic testing framework, where we use dynamically learned ordering constraints over shared object accesses to select only high-risk interleavings for test execution. An interleaving is of high-risk if it has not been covered by the ordering constraints, meaning that it has concurrency scenarios that have not been tested. Our method consists of two components. First, we utilize dynamic information collected from good test runs to learn ordering constraints over the memory-accessing and synchronization statements. These ordering constraints are treated as likely invariants since they are respected by all the tested runs. Second, during the process of systematic testing, we use the learned ordering constraints to guide the selection of interleavings for future test execution. Our experiments on public domain multithreaded C/C++ programs show that, by focusing on only the high-risk interleavings rather than enumerating all possible interleavings, our method can increase the coverage of important concurrency scenarios with a reasonable cost and detect most of the concurrency bugs in practice. Chao Wang 0001, Mahmoud Said, Aarti Gupta |
ICSE | 2 |
| 2009 | Offline symbolic analysis for multi-processor execution replayabstractAbility to replay a program's execution on a multi-processor system can significantly help parallel programming. To replay a shared-memory multi-threaded program, existing solutions record its program input (I/O, DMA, etc.) and the shared-memory dependencies between threads. Prior processor based record-and-replay solutions are efficient, but they require non-trivial modifications to the coherency protocol and the memory sub-system for recording the shared-memory dependencies. Mahmoud Said, Satish Narayanasamy, Zijiang Yang 0006, Cristiano Pereira |
MICRO | 2 |