EDBT 2026 Demo / reviewers in the wild / expert
Virginie Grandgirard
dblp:42/8910
· DBLP profile ↗
4ranked-venue papers
0as first author
0since 2021 · last 2020
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
GPUs and heterogeneous computing · 36% High-performance computing · 28% Hardware accelerators and domain-specific architectures · 28% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures
accelerator optimization |
0.3 | 1 | 2017 | Optimization of Fusion Kernels on Accelerators with Indirect or Strided Memory Access Patterns · IEEE Trans. Parallel Distributed Syst. 2017 |
GPUs and heterogeneous computing › GPU memory management
GPU memory access optimization |
0.3 | 1 | 2017 | Optimization of Fusion Kernels on Accelerators with Indirect or Strided Memory Access Patterns · IEEE Trans. Parallel Distributed Syst. 2017 |
High-performance computing
stencil computation |
0.3 | 1 | 2017 | Optimization of Fusion Kernels on Accelerators with Indirect or Strided Memory Access Patterns · IEEE Trans. Parallel Distributed Syst. 2017 |
Storage systems
data layout |
0.1 | 1 | 2017 | Optimization of Fusion Kernels on Accelerators with Indirect or Strided Memory Access Patterns · IEEE Trans. Parallel Distributed Syst. 2017 |
GPUs and heterogeneous computing
GPU computing |
0.1 | 1 | 2017 | Optimization of Fusion Kernels on Accelerators with Indirect or Strided Memory Access Patterns · IEEE Trans. Parallel Distributed Syst. 2017 |
Methods — techniques the papers use, named apart from their topics
temporal blocking · 0.3register reuse · 0.3data layout transformation · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | Overlapping communications in gyrokinetic codes on accelerator-based platformsabstractSummary Communication and computation overlapping techniques have been introduced in the five‐dimensional gyrokinetic codes GYSELA and GKV. In order to anticipate some of the exa‐scale requirements, these codes were ported to the modern accelerators, Xeon Phi KNL and Tesla P 100 GPU. On accelerators, a serial version of GYSELA on KNL and GKV on GPU are respectively 1.3× and 7.4× faster than those on a single Skylake processor (a single socket). For the scalability, we have measured GYSELA performance on Xeon Phi KNL from 16 to 512 KNLs (1024 to 32k cores) and GKV performance on Tesla P 100 GPU from 32 to 256 GPUs. In their parallel versions, transpose communication in semi‐Lagrangian solver in GYSELA or Convolution kernel in GKV turned out to be a main bottleneck. This indicates that in the exa‐scale, the network constraints would be critical. In order to mitigate the communication costs, the pipeline and task‐based overlapping techniques have been implemented in these codes. The GYSELA 2D advection solver has achieved a 33% to 92% speed up, and the GKV 2D convolution kernel has achieved a factor of 2 speed up with pipelining. The task‐based approach gives 11% to 82% performance gain in the derivative computation of the electrostatic potential in GYSELA. We have shown that the pipeline‐based approach is applicable with the presence of symmetry, while the task‐based approach can be applicable to more general situations. Yuuichi Asahi, Guillaume Latu, Julien Bigot, Shinya Maeyama, Virginie Grandgirard, Yasuhiro Idomura |
Concurr. Comput. Pract. Exp. | 5 |
| 2018 | Scaling and Optimizing the Gysela Code on a Cluster of Many-Core ProcessorsabstractThe current generation of the Xeon Phi Knights Landing (KNL) processor provides a highly multi-threaded environment on which regular programming models such as MPIjopenMP can be used. Many factors impact the performance achieved by applications on these devices: one of the key points is the efficient exploitation of SIMD vector units, and one another is the memory access pattern. Works have been conducted to adapt a plasma turbulence application, namely Gysela, for this architecture. A set of different techniques have been used: standard vectorization techniques, auto-tuning of one computation kernel, switching to high-order scheme. As a result, KNL execution times have been reduced by up to a factor 3. This effort has also permitted to gain a speedup of 2x on Broadwell architecture and 3x on Skylake. Nice scalability curves up to a few thousands cores have been obtained on a strong scaling experiment. Incremental work meant a large payoff without resorting to using low-level intrinsics. Guillaume Latu, Yuuichi Asahi, Julien Bigot, Tamas B. Fehér, Virginie Grandgirard |
SBAC-PAD | 5 |
| 2017 | Optimization of Fusion Kernels on Accelerators with Indirect or Strided Memory Access PatternsabstractThis paper describes optimization for high-dimensional stencil computations on accelerators involving complex memory access patterns, which appear in five dimensional fusion plasma turbulence codes, GYSELA and GT5D. They include different types of memory access patterns, the indirect memory access in GYSELA with a Semi-Lagrangian scheme and the strided memory access in GT5D with a Finite-Difference scheme. We focus on the affinity of the memory access patterns to accelerators such as GPGPUs and Xeon Phi coprocessors. On both devices, the Array of Structure of Array (AoSoA) data layout is preferable for contiguous memory accesses. It is shown that the effective local cache usage by improving spatial and temporal data locality is critical on Xeon Phi. On GPGPU, the texture memory usage improves the performance of the indirect memory accesses in the Semi-Lagrangian scheme. The reuse of registers by taking account of the physical symmetry of the Finite-Difference scheme reduces the amount of memory accesses. Through these optimizations, we achieve acceleration of 3.9 (8.1) on Xeon Phi (GPGPU) for the Semi-Lagrangian scheme and of 1.4 (3.9) on Xeon Phi (GPGPU) for the Finite-Different scheme with respect to the fully optimized codes on Sandy Bridge. Yuuichi Asahi, Guillaume Latu, Takuya Ina, Yasuhiro Idomura, Virginie Grandgirard, Xavier Garbet |
IEEE Trans. Parallel Distributed Syst. | 5 |
| 2015 | Toward memory scalability of GYSELA code for extreme scale computersabstractSummary Gyrokinetic simulations lead to huge computational needs. Up to now, the Semi‐Lagrangian code GYSELA performed large simulations using up to 65k cores. To understand more accurately the nature of plasma turbulence, finer resolutions are necessary, which make GYSELA a good candidate to exploit the computational power of future extreme scale machines. Among the Exascale challenges, the less memory per core is one of the most critical issues. This paper deals with memory management in order to reduce the memory peak and presents a general method to understand the memory behavior of an application when dealing with very large meshes. This enables us to extrapolate the behavior of GYSELA for expected capabilities of extreme scale machines. Copyright © 2014 John Wiley & Sons, Ltd. Fabien Rozar, Guillaume Latu, Jean Roman, Virginie Grandgirard |
Concurr. Comput. Pract. Exp. | 4 |