This paper describes a method of automatic placement for standard cells (polycells) that yields areas within 10-20 percent of careful hand placements. The method is based on graph partitioning to identify groups of modules that ought to be close to each other, and a technique for properly accounting for external connections at each level of partitioning. The placement procedure is in production use as part of an automated design system; it has been used in the design of more than 40 chips, in CMOS, NMOS, and bipolar technologies.

A new form of symbolic layout for integrated circuits is coupled with a mask compaction procedure which removes excess space while guaranteeing that all design rules are met. Tradeoffs between X and Y compaction are made based on critical path information. Two types of compaction are used to minimize mask area and computer run-time. Additional procedures reduce mask area by inserting jogs at strategic locations in the layout. A partitioned data base is used to store mask data in a hierarchical manner. The symbolic layout and mask compaction procedures require only 30 to 50 percent of the time traditionally needed to do equivalent hand layouts.