Conventional deep learning (DL) model compression methods affect all input samples equally. However, as samples vary in difficulty, a dynamic model that adapts computation based on sample complexity offers a novel perspective for compression and scaling. Despite this potential, existing dynamic techniques are typically monolithic and have model-specific implementations, limiting their generalizability as broad compression and scaling methods. Additionally, most deployed DL systems are fixed, and unable to adjust once deployed. This paper introduces DyCE, a dynamically configurable system that can adjust the performance-complexity trade-off of a DL model at runtime without needing re-initialization or re-deployment. DyCE achieves this by adding exit networks to intermediate layers, thus allowing early termination if results are acceptable. DyCE also decouples the design of exit networks from the base model itself, enabling its easy adaptation to new base models. We also propose methods for generating optimized configurations and determining exit network types and positions for dynamic trade-offs. By enabling simple configuration switching, DyCE enables fine-grained performance-complexity tuning in real-time. We demonstrate the effectiveness of DyCE through image classification tasks using deep convolutional neural networks (CNNs). DyCE significantly reduces computational complexity by 26.2% for ResNet 152 , 26.6% for ConvNextv2 tiny and 32.0% for DaViT base on ImageNet validation set, with accuracy reductions of less than 0.5%. • Effectively compress the computational complexity of deep learning models. • Dynamically Scale any AI model and select a complexity-performance tradeoff point for the model in run-time. • Enable early exiting on any existing deep learning models by attaching tiny exits. • Generates the best early-exit configuration in a multi-exit system for various trade-off preferences.

This paper introduces TinySaver, an early-exit-like dynamic model compression approach which employs tiny models to substitute large models adaptively. Distinct from traditional compression techniques, dynamic methods like TinySaver can leverage the difficulty differences to allow certain inputs to complete their inference processes early, thereby conserving computational resources. Most existing early exit designs are implemented by attaching additional network branches to the model’s backbone. Our study, however, reveals that completely independent tiny models can replace a substantial portion of the larger models’ job with minimal impact on performance. Employing them as the first exit can remarkably enhance computational efficiency. By searching and employing the most appropriate tiny model as the computational saver for a given large model, the proposed approaches work as a novel and generic method to model compression. This finding will help the research community in exploring new compression methods to address the escalating computational demands posed by rapidly evolving AI models. Our evaluation of this approach in ImageNet-1k classification demonstrates its potential to reduce the number of compute operations by up to 90%, with only negligible losses in performance, across various modern vision models.

This paper conducts a detailed analysis of the impact of channel charge injection on the capacitive digital-to-analog (DAC) block in successive-approximation register (SAR) analog-to-digital converters (ADCs). It introduces a CAD tool for distinguishing various non-idealities, quantifying channel charge injection across all possible binary output codes. It enables the implementation of more effective compensation methods rather than relying on simple dummy switches by detecting most effective switches. All simulations are conducted using Cadence TSMC 130nm CMOS technology and MATLAB software, implying on 5 to 7 dB degradation in SNDR when considering the effect of channel charge injection in 6, 9, and 12-bit typical SAR ADCs.

This paper proposes a time-domain mixed-signal computing architecture for Matrix-Vector Multiplication suited for embedded in-memory computing applications. The system leverages the low data rate of sensors’ data in embedded AI applications to target an energy-efficient implementation of the matrix-vector multiplication array. The mixed-signal computing scheme relies on incremental time-domain multiply-and-accumulate operations using switched current sources. The concept is demonstrated on a 28nm FDSOI prototype chip of a 100$\times $4 compute array that shows a 15.8TOPS/W energy efficiency for 5-bit MAC operations. Extrapolating the array to 100$\times $100 computing units leads to a 99.2TOPS/W energy efficiency.

Sensor Networks (SN) could be defined as networks of autonomous devices that can sense and/or act on physical or environmental conditions cooperatively. In sensor networks, data is typically sensed and sent toanaggregator thatwill process it with local AI or send it to a cloud with larger AI. This centralized architecture has drawbacks such as the aggregator having to receive and process a potentially huge amount of data, which results in power consumption that can be significant. In addition, the transmission of all the sensor data results in extra consumption of energy due to communication. To reduce the impact of this last point, on-edge computing allows data to be pre-processed at the sensor level. It is often used in the architecture of distributed sensor networks in which each node receives data from other nodes in the network and processes it with its local data. In this work, a distributed sensor network model aims to solve this problem while reducing the impact of data transmission on energy consumption. The proposed model is able to reduce the number of transmitted bits per node by 90% in a node-to-node directed communication scenario. It is also capable of working with different AI paradigms depending on the required balance between energy consumption, application configurability, and accuracy. Finally, this model is capable of converging even in a network without complete interconnections between nodes.

Cardiovascular diseases can be detected early by analyzing the electrocardiogram of a patient using wearable systems. In the context of smart sensors, detecting arrhythmias with good accuracy and ultra-low power consumption is required for long-term monitoring. This paper presents a novel cardiac arrhythmia classification method based on antidictionaries. The features are sequences of consecutive slopes generated from the input signal's event-driven processing. The proposed system shows an average detection accuracy of 98% while offering an ultra-low complexity. This antidictionary-based method is also particularly suited to imbalanced datasets since the antidictionaries are created exclusively from heartbeats classified as normal beats.

In this article, non-uniformly sampled electrocardiogram (ECG) signals obtained from level-crossing analog-to-digital converters (LC-ADCs) are analyzed for event-driven classification and compression performance. The signal compression results show that it is important to assess the distortion in eventdriven signals when simulating LC-ADC models, especially at lower resolutions and larger quantization steps. The effects of varying the LC-ADC parameters for the application of cardiac arrhythmia classifiers are also assessed using an artificial neural network (ANN) and the MIT-BIH Arrhythmia Database. In comparison with uniformly-sampled data, it is possible to achieve comparable classification accuracy at a much lower complexity with event-driven ECG signals. The results show the best eventdriven model achieves over 97% accuracy with 79% reduction in ANN complexity with signal-to-distortion ratio (S/D)>21dB. For S/D<; 21dB, the best event-driven model achieves 93% accuracy with a 96% reduction in ANN complexity. An open-source event-driven arrhythmia database is also presented.

Sharing a common clock signal among the nodes is crucial for communication in synchronized networks. This work presents a heartbeat-based synchronization scheme for body-worn nodes. The principles of this coordination technique combined with a puncture-based communication method are introduced. Theoretical models of the hardware blocks are presented, outlining the impact of their specifications on the system. Moreover, we evaluate the synchronization efficiency in simulation and compare with a duty-cycled receiver topology. Improvement in power consumption of at least 26% and tight latency control are highlighted at no cost on the channel availability.

The design of a baseband decision feedback equalizer, featuring a continuous-time digital delay line, is discussed within the context of a wireless, Line-Of-Sight, communication scenario over the 60-GHz band. BER simulations advocate for a critical-tap cancellation scheme, which leads to the realization of an equalizer featuring a small number of taps. A two-step configurable architecture is suggested as the equalizer's feedback path, in order to mitigate the loss of robustness that is caused by the absence of the clock. Simulations reveal the system's channel-dependent power consumption character and a delay line power consumption reduction of 3 to 4 times, when compared with its clocked counterpart.

This paper presents a 60GHz heterodyne receiver architecture with IF sub-sampling. A particular arrangement of the frequency plan allows anti-alias filtering by the charge-domain subsampler. Down-conversion, channel filtering and IQ demodulation are merged into a unique operator without any extra cost in terms of area and power consumption. The proposed architecture is able to receive up to 4 bonded channels and complies with the requirements of the standards for 60GHz wireless communications. The result of this study shows that subsampling is a good candidate for low power and configurable receivers for mmW wireless communications.

This paper presents a transmitter architecture able to manage its spurious emissions over a wide bandwidth. The architecture is based on a multiple-path polar transmitter with digital power amplifiers (DPA). The paths work at different sample rates, thus producing spectral images located at different frequencies. This multirate implementation generates more spurious images than conventional architectures, but with reduced image power. This leads to a significant signal-to-spurious improvement over a wide bandwidth. Using the proposed architecture in a transmitter targeting LTE standard, the spurious emissions are reduced by 20dB over a frequency band from 800MHz to 3GHz, allowing to remove any analog filter stages to respect the standard specifications.