The integrated circuit for 3D chip placement has attracted much attention in recent years, but its complex netlist structure poses significant challenges in optimizing 3D chip placement. However, the current algorithms for 3D chip placement have not considered further optimizing the placement, and existing location-based coding strategies have failed to effectively guide the optimization of standard cell placement. Therefore, a multi-objective optimization method with a mixedcoding strategy (MOMC3D) is proposed for standard cells in 3D chip placement, focusing on the adjustment of standard cell positions. The proposed MOMC3D algorithm includes the following three contributions. Firstly, a cell-netlist mixed-coding (CNMC) strategy to code the information of standard cells and netlist separately is designed to represent placement information of the current chip. Secondly, a max-min net length exchange (MMNE) crossover strategy and a large net boundary reduction (LNBR) mutation strategy are designed to reduce the halfperimeter wire length (HPWL). Thirdly, the 3D chip placement optimization is modeled as a multi-objective optimization problem, using an improved non-dominated sorting genetic algorithm II (NSGA-II) multi-objective evolutionary framework to iterate the HPWL and the number of terminals. Compared to existing location-based coding strategies, the CNMC strategy achieved a 9.54% reduction in HPWL and a 17.18% reduction in the number of terminals in the legally compliant placement of ICCAD 2023 contest case 2. Furthermore, compared to other existing multi-objective optimization algorithms and reinforcement learning algorithms, the MOMC3D algorithm reduced the HPWL and the number of terminals by 11.59% and 8.41%, respectively.