As chip complexity continues to grow, traditional rule-based EDA tools face increasing challenges in optimizing power, performance, and area (PPA). There is a pressing need for a foundation model in chip layout to leverage large-scale historical design data for unified and intelligent physical design. We propose iPCL (pre-training for chip layout), a comprehensive framework that integrates placement and routing generation, metric evaluation and optimization. iPCL consists of layout symbolization, multimodal pre-training, solution generation and selection, and post-processing stages, forming a scalable and automated design pipeline. iPCL reduces design iteration time, supports multi-layout generation, and automatically selects optimal solutions through lightweight ECO refinement. Two versions are developed: iPCL-R, which generates routing layouts with performance comparable to commercial tools while reducing design time by 55.7%; and iPCL-M, which delivers $336 \times$ faster and more accurate metric evaluation than open-source EDA, achieving about 5% better optimization results than commercial tools.

Recent research has demonstrated that artificial intelligence (AI) can assist electronic design automation (EDA) in improving both the quality and efficiency of chip design. But current AI for EDA (AI-EDA) infrastructures remain fragmented, lacking comprehensive solutions for the entire data pipeline from design execution to AI integration. Key challenges include fragmented flow engines that generate raw data, heterogeneous file formats for data exchange, non-standardized data extraction methods, and poorly organized data storage. This work introduces a unified open-source library for EDA (AiEDA) that addresses these issues. AiEDA integrates multiple design-to-vector data representation techniques that transform diverse chip design data into universal multi-level vector representations, establishing an AI-aided design (AAD) paradigm optimized for AI-EDA workflows. AiEDA provides complete physical design flows with programmatic data extraction and standardized Python interfaces that bridge EDA datasets and AI frameworks. Leveraging the AiEDA library, we generate iDATA, a 600GB dataset of structured data derived from 50 real chip designs (28nm), and validate its effectiveness through five representative AAD tasks spanning prediction, generation, and optimization. The code of AiEDA is publicly available at https://github.com/OSCC-Project/AiEDA, providing a foundation for future AI-EDA research.

Placement is a critical and time-consuming step in very-large-scale integration (VLSI) design flow. As placement methods continue to be researched, they introduce more parameters, making current methods for configuring parameters heavily reliant on human experience for each design. This article proposes a novel cross-design parameter optimization method, iPO, to accelerate parameter tuning without human involvement in different placement engines (like iEDA-iPL and DREAMPlace). Specifically, we introduce a heuristic strategy called Constant Liar to accelerate parameter tuning, allowing us to optimize parameters concurrently on different machines. Our research indicates that optimizing parameters for every design is time-consuming. To address the inefficiency of parameter tuning, we propose a cross-design parameter transfer learning strategy. This strategy measures the cosine similarity between designs in collaboration with a graph embedding algorithm representing netlists and cells. Compared with DREAMPlace on ISPD2015 benchmarks, our method achieves average improvements of 9.8% in half-perimeter wirelength (HPWL) and 12.0% in route congestion. When compared with AutoDMP, iPO shows an average improvement of 11% in HPWL and 12.3% in congestion, along with a 3.49× speed-up in the number of search iterations. Furthermore, we extended our experiments to the iEDA-28nm benchmarks, showing average improvements of 4.7%, 2.7% and 2.8% in HPWL, worst negative slack (WNS) and total negative slack (TNS), respectively, compared with iEDA-iPL. Finally, our ablation studies on parallelization demonstrate that using 10 parallel processes results in approximately an 18× speed-up compared with using a single process.

The increasing complexity of digital circuits and the limitations of heuristic methods have led to growing interest in applying Machine Learning (ML) to Logic Synthesis (LS). ML provides a promising paradigm shift by implementing automated, scalable, and data-driven optimization strategies. This survey provides a comprehensive overview of the latest studies on ML approaches in LS, offering a deep understanding of the fundamental ML methods, and analyzing their strengths and limitations through systematic comparisons. We categorize existing works into two main types: ML-Assistance methods aiming at predicting performance metrics and reducing the cost of traditional simulations, and ML-Agent methods directly replacing heuristic processes in the LS flow. We further analyze ML methods and applications in different LS stages, including Boolean circuit generation, Boolean circuit analysis, logic optimization, and technology mapping, showing great achievements and improvement in exploring non-linear design spaces and discovering new optimization strategies. Finally, we discuss the challenges and limitations in the current situation and further provide a vision of future directions in LS.