EDBT 2026 Demo / reviewers in the wild / expert
Zaitian Chen
dblp:426/0191
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2026
0009-0005-0464-5345ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 25% Electronic design automation · 25% High-performance computing · 25% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
circuit simulation |
1.0 | 1 | 2026 | Real-Time Compensation Framework for Large-Scale ReRAM-Based Sparse LU Factorization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026 |
Memory systems › in-memory computing
ReRAM-based accelerator |
1.0 | 1 | 2026 | Real-Time Compensation Framework for Large-Scale ReRAM-Based Sparse LU Factorization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026 |
High-performance computing › sparse linear solver
sparse LU factorization |
1.0 | 1 | 2026 | Real-Time Compensation Framework for Large-Scale ReRAM-Based Sparse LU Factorization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026 |
Methods — techniques the papers use, named apart from their topics
supernodal LU factorization · 1.0sparse matrix modeling · 1.0anderson acceleration · 1.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Real-Time Compensation Framework for Large-Scale ReRAM-Based Sparse LU FactorizationabstractRecently, resistive switching random access memory (ReRAM)-based hardware accelerators have demonstrated unprecedented performance compared to digital accelerators. However, due to limitations in the manufacturing process and largescale integration, several significant non-ideal effects, including IR-Drop, Stuck-At-Fault, and device noises in real ReRAM-based crossbar arrays, are typically incurred. These non-ideal effects degrade signal integrity and performance, particularly in crossbar structures used for building high-density ReRAMs. Therefore, finding a fast and efficient software solution that can predict the effects of IR-drop without involving expensive hardware is highly desirable. In this work, addressing the main limitations of existing simulation methods, such as slow speed and high resource costs, we propose an efficient analysis of large-scale ReRAM crossbar arrays and the corresponding non-ideal factors based on sparse matrix modeling. We classify non-ideal factors into linear (e.g., IR-drop) and nonlinear categories (e.g., shot noise). For linear factors, super-nodal sparse LU factorizations are used to solve. The array-level results show that compared to SPICE simulation, our method achieves a numerical solution accuracy of 10.15 with 506.8 1253.3× faster and 17.46 42934.3× reduced memory usage. For nonlinear factors, we propose two solutions based on different requirements. In one method, we obtain an approximate initial solution by solving a linear system while disregarding the nonlinear contributions and subsequently apply an extended Anderson acceleration method to solve the nonlinear equation, which is suitable for high-precision solutions. Another method simplifies the nonlinear equation into an equivalent linear form. Theoretical validation confirms the effectiveness of this method, significantly enhancing simulation speed while maintaining accuracy. Moreover, we build a high-precision ReRAM accelerator architecture with real-time compensation. Experimental results demonstrate that the proposed architecture effectively mitigates accuracy loss caused by non-ideal factors. Zaitian Chen, Bei Yu 0001, Song Chen 0001, Yi Kang, Qi Xu 0004 |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |