EDBT 2026 Demo / reviewers in the wild / expert
Nastaran Hajinaza
dblp:426/3117
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2025
0000-0003-2817-0223ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 100% | |
| Software engineering, system software, and programming languages
1 paper |
Operating systems · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › memory management › virtual memory
address translation |
0.9 | 1 | 2025 | Learning to Walk: Architecting Learned Virtual Memory Translation · MICRO 2025 |
Memory systems › memory management › virtual memory
page table |
0.9 | 1 | 2025 | Learning to Walk: Architecting Learned Virtual Memory Translation · MICRO 2025 |
Memory systems › memory management
virtual memory |
0.9 | 1 | 2025 | Learning to Walk: Architecting Learned Virtual Memory Translation · MICRO 2025 |
Operating systems › resource management
memory management |
0.3 | 1 | 2025 | Learning to Walk: Architecting Learned Virtual Memory Translation · MICRO 2025 |
Methods — techniques the papers use, named apart from their topics
learned index · 1.7fixed-point arithmetic · 1.7RTL synthesis · 1.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Learning to Walk: Architecting Learned Virtual Memory TranslationabstractThe rise in memory demands of emerging datacenter applications has placed virtual memory translation in the spotlight, exposing it as a significant performance bottleneck.To address this problem, this paper introduces Learned Virtual Memory (LVM), a page table structure that effectively provides optimal single-access address translation.LVM is founded on a novel learned index model that dynamically adapts the address translation procedure based on the characteristics of an application's virtual address space.Furthermore, LVM's learned index requires minimal memory space, does not impose stringent physical contiguity requirements, enjoys high cacheability in the MMU, efficiently supports insertions, and relies on simple fixed-point arithmetic.Finally, LVM supports all features of virtual memory, including multiple page sizes.We evaluate LVM with a set of operating system (OS) extensions in Linux, RTL synthesis, and full-system simulations across a wide range of workloads.LVM reduces the address translation overhead by an average of 44% over radix page tables, while reducing the page walk cache area required by 1.5×.Overall, LVM achieves a 2-27% speedup in application execution time and is within 1% of an ideal page table. Kaiyang Zhao 0002, Xenia Xu, Dan Schatzberg, Nastaran Hajinaza, Rupin Vakharwala, Andy Anderson, Dimitrios Skarlatos 0002 |
MICRO | 5 |