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Ying-Sheng Huang

dblp:426/3300 · DBLP profile ↗
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2ranked-venue papers
1as first author
2since 2021 · last 2026
0009-0005-2604-9421ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware reliability and fault tolerance · 77% Integrated circuit design · 23%
Network and information security
1 paper
Cryptographic primitives and cryptanalysis · 100%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance
error detection
1.012026
CRC-Based Error Detection Mechanism for Multiplicative Inverse in Redundant Basis S -Box · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Cryptographic primitives and cryptanalysis › cryptographic implementation
s-box implementation
0.312026
CRC-Based Error Detection Mechanism for Multiplicative Inverse in Redundant Basis S -Box · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026

Methods — techniques the papers use, named apart from their topics

cyclic redundancy check · 2.0
YearPublicationVenuePosition
2026 High-Performance AES-GCM Hardware via Circuit and Architecture Co-Design of AES and GHASH
Chia-Chou Chuang, Chuan-Kai Su, Ying-Sheng Huang, Da-Huei Lee, Pei-Yin Chen
ISCAS3
2026 CRC-Based Error Detection Mechanism for Multiplicative Inverse in Redundant Basis S -Box
Ying-Sheng Huang, Chia-Chou Chuang, Chien-Chung Ho, Pei-Yin Chen
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1