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Juyoung Seok

dblp:426/3780 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2025
0009-0005-0646-8303ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 80% GPUs and heterogeneous computing · 20%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › memory management › virtual memory
address translation
0.912025
SoftWalker: Supporting Software Page Table Walk for Irregular GPU Applications · MICRO 2025
GPUs and heterogeneous computing
GPU memory management
0.912025
SoftWalker: Supporting Software Page Table Walk for Irregular GPU Applications · MICRO 2025
Memory systems › memory management › virtual memory
page table walk
0.912025
SoftWalker: Supporting Software Page Table Walk for Irregular GPU Applications · MICRO 2025
Memory systems › virtual memory management
TLB miss handling
0.912025
SoftWalker: Supporting Software Page Table Walk for Irregular GPU Applications · MICRO 2025
Memory systems › memory management
virtual memory
0.912025
SoftWalker: Supporting Software Page Table Walk for Irregular GPU Applications · MICRO 2025

Methods — techniques the papers use, named apart from their topics

software page table walker · 0.9MSHR expansion · 0.9
YearPublicationVenuePosition
2025 SoftWalker: Supporting Software Page Table Walk for Irregular GPU Applications
abstract
Address translation has become a significant and growing performance bottleneck in modern GPUs, especially for emerging irregular applications with high TLB miss rates.The limited concurrency of hardware Page Table Walkers (PTWs), due to their small and fixed number, causes severe contention and substantial queueing delays under high translation pressure, which significantly degrades performance.This paper introduces SoftWalker, a novel, scalable, and flexible framework that fundamentally shifts the GPU page table walking from fixed-function hardware to software execution.SoftWalker leverages the GPU's massive thread-level parallelism by dynamically dispatching specialized, lightweight software threads running on GPU cores to handle TLB misses requiring page table walks.In addition, to expand L2 TLB MSHR capacity on demand, SoftWalker incorporates In-TLB MSHRs, a key innovation that repurposes underutilized L2 TLB entries to track outstanding misses when existing MSHRs are saturated.By alleviating MSHR-induced contention, this design preserves the key advantage of highly parallel page table walking in software.SoftWalker enables thousands of concurrent page table walks, significantly reducing PTW-level contention and translation queueing delays.As a result, it achieves an average reduction of 72.8% in page walk latency and delivers an average speedup of 2.24× (3.94× for irregular workloads).
Sungbin Jang, Junhyeok Park 0001, Osang Kwon, Juyoung Seok, Seokin Hong
MICRO6