Particle-in-Cell (PIC) simulations devote most cycles to particle-grid interactions, and their fine-grained atomic updates become a severe bottleneck on traditional many-core CPUs. The evolution of CPU architectures, particularly the integration of specialized Matrix Processing Units (MPUs) designed for efficient matrix outer-product operations, presents a paradigm shift and an opportunity to alleviate these bottlenecks. Capitalizing on this architectural advancement, this work focuses on adapting the critical current deposition step in PIC simulations to this new matrix-centric computational model.

Particle-in-Cell (PIC) simulations are fundamental to plasma physics but often suffer from limited scalability due to particle–grid interaction bottlenecks and particle redistribution costs. Specifically, the particle–grid interaction computations have not taken full advantage of the emerging Matrix Processing Units (MPUs), the particle motion introduces irregular memory accesses, and the bulk-synchronous redistribution further destroys long-term data locality thereby limiting parallel efficiency. To address these inefficiencies, we present POLAR-PIC, a co-designed framework for large-scale PIC simulations that (i) reformulates Field Interpolation into an MPU-friendly outer-product form, (ii) maintains a physically ordered particle layout to preserve memory contiguity, and (iii) overlaps particle communication with Deposition to hide redistribution overhead. The evaluation on the pilot system of an Exascale supercomputer demonstrates that POLAR-PIC accelerates the entire particle-processing phase by up to 10.9 × in uniform plasma and 4.4 × in real-world laser-ion acceleration scenarios compared to the native WarpX reference pipeline on LX2. Ablation studies reveal that the speedups achieved by Interpolation and Deposition are 8.0 × and 13.2 × , respectively, and the asynchronous communication design sustains a \(99.1\%\) overlap ratio. In cross-platform comparisons, POLAR-PIC achieves \(13.2\%\) of theoretical peak efficiency on the CPU-based LS system, while WarpX reaches \(9.6\%\) on NVIDIA A800 GPUs. Notably, the scalability evaluation demonstrates that POLAR-PIC maintains \(67.5\%\) weak scaling efficiency on over 2 million cores under high-migration dynamic workloads, highlighting the importance of holistic co-design for future matrix-centric HPC systems.

Large-scale simulation of Spiking Neural Networks (SNNs) on supercomputers is pivotal for unraveling the mechanisms of brain function and advancing brain-inspired intelligence. However, efficiently mapping billions of neurons onto distributed nodes presents a significant challenge due to the heterogeneity of neuronal activities and complex, irregular network connectivity. While static partitioning strategies perform well in stable states, they often fail under metastable neurodynamics where theoretical models cannot accurately predict neuronal firing rates, leading to severe load imbalance. To address this, we propose TADS (Trend-Aware Dynamic load balancing with Delay-Sharded graph infrastructure), a framework tailored for large-scale SNN simulations. First, we identify the specific failure modes of static partitioning under metastable dynamics, establishing the necessity for runtime intervention. Second, we introduce a trend-aware dynamic load balancing strategy. By analyzing the temporal evolution of loads, this approach effectively distinguishes persistent imbalance from transient fluctuations, thereby avoiding unnecessary migrations caused by momentary jitter. Third, we design a delay-sharded graph infrastructure that leverages synaptic delays to parallelize graph modifications, significantly reducing the overhead associated with dynamic load balancing. Experimental results on the Tianhe-Xingyi supercomputer demonstrate that TADS effectively handles metastable scenarios, achieving up to 2.13 × speedup over state-of-the-art static partitioning methods, while sustaining 1.58 × performance improvement at the largest evaluated scale of 192 nodes.