Spin-orbit torque magnetic tunnel junction (SOT-MTJ) devices have gained significant attention for energy-efficient computing, particularly in Logic-in-Memory (LiM) architectures. However, conventional SOT-MTJ-based write circuits suffer from excessive power dissipation due to the reliance on externally generated Spin Hall Effect (SHE) pulses, necessitating complex synchronization and additional circuit overhead. This work introduces a novel self-SHE pulse generation technique that eliminates the need for an external SHE pulse, simplifying the circuit design and significantly reducing energy consumption. Furthermore, the proposed design leverages 2D material-based SOT-MTJs, which exhibit superior charge-to-spin conversion efficiency, thereby enhancing write performance. The proposed write circuit is integrated into a 1-bit Arithmetic Logic Unit (ALU), which is further extended to a 4-bit ALU to demonstrate scalability in LiM applications. Simulation results using 45nm CMOS technology and Verilog-A models for 2D SOT-MTJs indicate that the proposed write circuit achieves a 16.049% improvement in area efficiency and a 20.72% reduction in energy consumption compared to conventional SHE-assisted SOT-MTJ write circuits. Additionally, the full adder incorporating the proposed write circuit demonstrates a 25.2% improvement in energy efficiency over existing designs. Monte Carlo simulations validate the robustness of the proposed approach under variations in oxide layer and free layer thickness. By eliminating external SHE pulse requirements and utilizing 2D SOT-MTJ technology, this work presents a significant advancement towards low-power, high-speed, and scalable spintronic computing architectures, making it a strong candidate for next-generation LiM-based processors.