EDBT 2026 Demo / reviewers in the wild / expert
Shiji Gao
dblp:429/2774
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2026
0009-0006-4777-4777ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
GPUs and heterogeneous computing · 50% Hardware accelerators and domain-specific architectures · 38% Reconfigurable computing and FPGAs · 12% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
GPUs and heterogeneous computing
heterogeneous architecture |
1.0 | 1 | 2026 | DFVG: A Heterogeneous Architecture for Speculative Decoding with Draft-on-FPGA and Verify-on-GPU · ASPLOS (2) 2026 |
Hardware accelerators and domain-specific architectures › efficient inference
speculative decoding |
1.0 | 1 | 2026 | DFVG: A Heterogeneous Architecture for Speculative Decoding with Draft-on-FPGA and Verify-on-GPU · ASPLOS (2) 2026 |
Reconfigurable computing and FPGAs
FPGA accelerator |
0.3 | 1 | 2026 | DFVG: A Heterogeneous Architecture for Speculative Decoding with Draft-on-FPGA and Verify-on-GPU · ASPLOS (2) 2026 |
GPUs and heterogeneous computing
GPU computing |
0.3 | 1 | 2026 | DFVG: A Heterogeneous Architecture for Speculative Decoding with Draft-on-FPGA and Verify-on-GPU · ASPLOS (2) 2026 |
Methods — techniques the papers use, named apart from their topics
speculative decoding · 1.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | DFVG: A Heterogeneous Architecture for Speculative Decoding with Draft-on-FPGA and Verify-on-GPU
Shaoqiang Lu, Yangbo Wei, Junhong Qian, Dongge Qin, Shiji Gao, Yizhi Ding, Xiao Shi 0001, Lei He 0001 |
ASPLOS (2) | 5 |