EDBT 2026 Demo / reviewers in the wild / expert
Ali Semi Yenimol
dblp:429/3038
· DBLP profile ↗
1ranked-venue papers
1as first author
1since 2021 · last 2026
0000-0002-0504-7137ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 77% Hardware accelerators and domain-specific architectures · 23% | |
| Theoretical computer science
1 paper |
Graph algorithms and graph theory · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
processing-in-memory |
1.0 | 1 | 2026 | CoGraf: Fully Accelerating Graph Applications with Fine-Grained PIM · ASPLOS (2) 2026 |
Graph algorithms and graph theory
graph processing |
1.0 | 1 | 2026 | CoGraf: Fully Accelerating Graph Applications with Fine-Grained PIM · ASPLOS (2) 2026 |
Hardware accelerators and domain-specific architectures
graph processing accelerator |
0.3 | 1 | 2026 | CoGraf: Fully Accelerating Graph Applications with Fine-Grained PIM · ASPLOS (2) 2026 |
Methods — techniques the papers use, named apart from their topics
tuple-based LLC coalescing · 2.0multi-DRAM column processing · 2.0bank-parallel PIM instructions · 2.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | CoGraf: Fully Accelerating Graph Applications with Fine-Grained PIMabstractProcessing-in-Memory (PIM) delivers enormous performance by taking advantage of internal DRAM bandwidth and parallelism. However, graph applications are difficult to adapt to PIM due to their irregular access patterns.We present the first Fine-Grained PIM (FGPIM) design that fully accelerates vertex-centric push-based graph applications by accelerating both their update (computing vertex updates) and apply (summing up the updates) phases. For the update phase, we design a tuple-based LLC that can coalesce at different granularities to group graph updates together and propose multi-DRAM column processing FGPIM instructions to match the cache coalescing to the row-level parallelism of the FGPIM. With this acceleration, the apply phase becomes the bottleneck, and we propose bank-parallel FGPIM instructions with predicates to allow FGPIM to accelerate the conditional updates as well. We achieve an average speedup in the region of interest of 1.8x/3x compared to naive FGPIM and 4.4x/9.8x compared to state-of-the-art non-PIM baseline (HBM2/DDR4), and DRAM energy reduction of 67%/86% and 88%/94%.These results show the importance of providing a complete solution that accelerates both the update and apply phases. Ali Semi Yenimol, Anirban Nag, Chang Hyun Park 0001, David Black-Schaffer |
ASPLOS (2) | 1 |