Hrishikesh Jedhe Deshmukh

dblp:429/3122 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2026
0009-0008-8222-4070ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 44% Processor architecture and microarchitecture · 44% Cloud and datacenter computing · 13%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › cache › CPU cache
instruction cache
1.012026
ICARUS: Criticality and Reuse based Instruction Caching for Datacenter Applications · ASPLOS (2) 2026
Cloud and datacenter computing › datacenter workloads
datacenter applications
0.312026
ICARUS: Criticality and Reuse based Instruction Caching for Datacenter Applications · ASPLOS (2) 2026

Methods — techniques the papers use, named apart from their topics

reuse-based caching · 1.0criticality-based replacement · 1.0
YearPublicationVenuePosition
2026 ICARUS: Criticality and Reuse based Instruction Caching for Datacenter Applications
abstract
Datacenter applications with huge code footprints suffer from front-end CPU bottlenecks even with a decoupled front-end. These applications are composed of complex system stacks with subtle interdependencies. One of the primary contributors to the front-end bottleneck is instruction misses at L2, which cause decode starvation. State-of-the-art L2 cache replacement policies, such as EMISSARY, utilize front-end criticality to identify instruction lines that cause decode starvation and attempt to keep those critical lines in L2. We observe that only 28.32% of the critical lines retain their criticality behavior, and a significant fraction of the critical instruction lines show dynamic behavior.
Vedant Kalbande, Hrishikesh Jedhe Deshmukh, Alberto Ros 0001, Biswabandan Panda
ASPLOS (2)2