Neural hardware accelerators have demonstrated notable energy efficiency in tackling tasks, which can be adapted to artificial neural network (ANN) structures. Research is currently directed toward leveraging resistive random-access memories (RRAMs) among various memristive devices. In conjunction with complementary metal-oxide semiconductor (CMOS) technologies within integrated circuits (ICs), RRAM devices are used to build such neural accelerators. In this study, we present a neural accelerator hardware design and verification flow, which uses a lookup table (LUT)-based Verilog-A model of IHP’s one-transistor-one-RRAM (1T1R) cell. In particular, we address the challenges of interfacing between abstract ANN simulations and circuit analysis by including a tailored Python wrapper into the design process for resistive neural hardware accelerators. To demonstrate our concept, the efficacy of the proposed design flow, we evaluate an ANN for the MNIST handwritten digit recognition task, as well as for the CIFAR-10 image recognition task, with the last layer verified through circuit simulation. Additionally, we implement different versions of a 1T1R model, based on quasi-static measurement data, providing insights on the effect of conductance level spacing and device-to-device variability. The circuit simulations tackle both schematic and physical layout assessment. The resulting recognition accuracies exhibit significant differences between the purely application-level PyTorch simulation and our proposed design flow, highlighting the relevance of circuit-level validation for the design of neural hardware accelerators.

Emerging non-volatile memories (eNVMs) such as resistive random-access memory (RRAM) offer an alternative solution compared to standard CMOS technologies for implementation of in-memory computing (IMC) units used in artificial neural network (ANN) applications. Existing measurement equipment for device characterisation and programming of such eNVMs are usually bulky and expensive. In this work, we present a compact size characterization platform for RRAM devices, including a custom programming unit IC that occupies less than 1 mm2of silicon area. Our platform is capable of testing one-transistor-one-RRAM (1T1R) as well as one-transistor-multiple-RRAM (1TNR) cells. Thus, to the best knowledge of the authors, this is the first demonstration of an integrated programming interface for 1TNR cells. The 1T2R IMC cells were fabricated in the IHP’s 130 nm BiCMOS technology and, in combination with other parts of the platform, are able to provide more synaptic weight resolution for ANN model applications while simultaneously decreasing the energy consumption by 50 %. The platform can generate programming voltage pulses with a 3.3 mV accuracy. Using the incremental step pulse with verify algorithm (ISPVA) we achieve 5 non-overlapping resistive states per 1T1R device. Based on those 1T1R base states we measure 15 resulting state combinations in the 1T2R cells.

In this research paper, a concept for a 225 GHz frequency quadrupler with phase control in local oscillator paths is investigated. By combining a 56.25 GHz phase shifter with a millimeter wave quadrupler, producing a 225GHz signal, a highly performant way of realizing phase control at up to sub-THz frequencies is studied. Locating the phase shifter in the sub 60GHz band both enhances the phase control and overall gain of the system. A phase control range of 330° is measured. With a de power consumption of 105mW, the system achieves a maximum output power of 0.16dBm and a maximum gain of 21dB outperforming the state of the art by 17dB and 25dB respectively. This results in a factor 40 and 2.5 improvement of drain and gain efficiency respectively. Additionally, the root mean square (rms) gain error is reduced to best in class value of 0.04 dB while maintaining a competitive rms phase error of 4.7°.

In this paper, a nonlinear analysis of cross- coupled super-regenerative oscillators (SROs) is presented. The start-up and decay envelopes of the oscillator output are studied in relation to the input. The SRO start-up time and the maximal achievable quenching frequency are investigated. For phase modulation purposes, the relation between the initial phases of the input and output signals is investigated. In addition, a frequency-domain analysis is performed to ease the characterization of circuit prototypes at frequencies where time-domain measurements are not possible. The analytical results are verified by circuit-level simulations and measurements of a 2.4-GHz SRO. This study provides design guidelines for the design of SROs in cross-coupled architectures and helps in determining the optimal system parameters when targeting both amplitude and phase modulations. To the authors' best knowledge, this is the first study investigating analytically the phase relation between the SRO input and output signals and the nonlinear large-signal behavior of SROs.

This paper presents the design and characterization of a low power 20 Gb/s 1:4 demultiplexer (Demux) in 45-nm SOI CMOS. For the design of the latch, which is used primarily inside the key building blocks of the 1:4 Demux, a power-speed optimized current-scaling methodology is provided. The results of an electromagnetic (EM) 3D field solver, which was used to simulate the high-frequency performance of the most critical data and clock paths inside the Demux, are presented. The designed 1:4 Demux uses a supply voltage of 1 V, dissipates a total of 77 mW of power, and occupies an active area of 0.122mm2. Among the reported inductorless CMOS 20 Gb/s 1:4 Demuxes, the presented Demux achieves the best energy figure of 3.8 pJ/bit.

This work presents an integrated low noise amplifier (LNA), based on an ac-coupled 7-stage common-emitter topology. An analysis on the basic transistor configurations is performed, to show the advantages of a common emitter chain for LNA designs. The circuit is intended for ultra-wideband wireless communication systems at 180 GHz (G-band) and offers a measured gain of 19 dB. The bandwidth of over 80 GHz is one of the highest reported. The simulated noise figure is 7.1 dB at 180 GHz and the group delay variation is below 7 ps. The input referred 1-dB compression point occurs above -30 dBm, while the total dc power consumption is 42 mW. The final chip occupies an area of 0.55 mm2and is implemented in a 130 nm SiGe BiCMOS process, which offers a maximum oscillation frequency fmaxof 450 GHz.

This brief presents a 4-bit digitally controlled differential delay element (DCDE) with high-speed and high-resolution capability, two challenging requirements in the design of delay elements. Two input bits, inside the differential current-mode logic (CML) DCDE, regulate its bias current and the resistive load, while the other two bits configure the output capacitive load enabling the presented DCDE to achieve a phase shift of 20 ps and an average resolution of 1.25 ps. Designed in 45-nm silicon-on-insulator (SOI) CMOS, the DCDE dissipates 4 mW of power under maximum biasing condition and can operate up to 10 Gb/s while adding only 0.6 ps of root-mean-square jitter to the delayed input. To the best of authors knowledge, the designed DCDE is the first 4-bit low-jitter 10-Gb/s variable-load CML DCDE offering a time resolution of 1.25 ps, making it a suitable candidate for high-speed and high-resolution applications.

In this paper a modified current switching cell suitable for binary current-steering digital-to-analog converters (DAC) is introduced. An extensive analysis based on the slew rate (SR) and input capacitance calculation is performed, and compared against circuit level simulations. The analysis is focused on the SR-induced bandwidth as it is a limiting factor for high-speed performance of binary DACs. It is shown that the proposed approach provides around 40% lower input capacitance and, consequently, more than 60% higher SR at high-current cells compared to a commonly utilized cascode differential pair. It also shows a closer capacitance ratio between the most significant and least significant bits, leading to closer dynamic response among DAC switches compared to a fully binary realization of DAC cells.

This paper presents a fully-differential frequency doubler integrated in 130 nm SiGe BiCMOS technology. To obtain a differential output signal, the conventional push-push topology is extended. The benefits of this approach are investigated with non-linear circuit analysis and discussed. While both the conventional push-push doubler and the Gilbert-cell doubler only suppress the odd harmonics, the extended topology enables the further suppression of the fourth harmonic. The circuit requires a set of phase-shifted versions of the input signal, which are generated on-chip with a polyphase filter. The proposed approach is validated with measurements of the fabricated circuit: an output power of -4 dBm at the 1 dB compression point with a -3 dB output bandwidth of 10 GHz from 55.6 GHz to 65.6 GHz is reported. With a low power consumption of 23.5 mW, a conversion gain of -15 dB and a fundamental suppression of 42 dB are achieved around the center frequency. A method to improve the conversion gain is discussed in the conclusion.