Neural rendering enables photorealistic scene re-construction but remains difficult to deploy on edge devices due to intensive computation, redundant sampling, and memory bandwidth constraints. This work presents a high-performance neural rendering accelerator for real-time embedded rendering. The proposed design integrates: (1) a dual-process backend with fused micro-MLPs to significantly improve sample processing efficiency, (2) multi-resolution spatial partitioning with adaptive ray clustering to exploit sparsity and achieve over 95% cache hit rate, and (3) a multi-level scheduling framework with proactive prefetching to reduce MLP stalls. Implemented on FPGA, the prototype achieves 94.7 FPS at 800×800 resolution with 6.4 W power consumption. An ASIC implementation in 28 nm technology sustains 440 FPS at 268 mW. Experimental results demonstrate state-of-the-art performance and energy efficiency while preserving rendering quality above 30 dB PSNR.

Neural radiance fields (NeRFs) have transformed 3-D reconstruction and rendering, facilitating photorealistic image synthesis from sparse viewpoints. This work introduces an explicit data reuse neural rendering (EDR-NR) architecture, which reduces frequent external memory accesses (EMAs) and cache misses by exploiting the spatial locality from three phases, including rays, ray packets (RPs), and samples. The EDR-NR architecture features a four-stage scheduler that clusters rays on the basis of$Z$-order, prioritize lagging rays when ray divergence happens, reorders RPs based on spatial proximity, and issues samples out-of-orderly (OoO) according to the availability of on-chip feature data. In addition, a four-tier hierarchical RP marching (HRM) technique is integrated with an axis-aligned bounding box (AABB) to facilitate spatial skipping (SS), reducing redundant computations and improving throughput. Moreover, a balanced allocation strategy for feature storage is proposed to mitigate SRAM bank conflicts. Fabricated using a 40-nm process with a die area of 10.5 mm2, the EDR-NR chip demonstrates a$2.41\times $enhancement in normalized energy efficiency, a$1.21\times $improvement in normalized area efficiency, a$1.20\times $increase in normalized throughput, and a 53.42% reduction in on-chip SRAM consumption compared with state-of-the-art accelerators.

Feature pyramid network (FPN) can highly improve the performance of object detection by extracting multiscale features. However, current FPN-based methods suffer from intrinsic correlation of local information loss in each feature map, which brings about the semantic information effective transmission problem. In addition, 1 × 1 convolution in lateral connection of FPN may cause spatial information loss. In this article, we propose a novel semantic and spatial information enhancing feature pyramid network (Dual SIE-FPN), which mainly focuses on alleviating multiscale hierarchical feature transmission loss and enhancing the feature representation. Specifically, Dual SIE-FPN contains three modules: Lateral Feature Enhancement (LFE), Global Attention Upsampling (GAU), and Multiple Information Compensation (MIC). LFE is designed to capture deep semantic representation and enhance channel information. GAU is established to make up for spatial information loss caused by upsampling, and transmit the high-level features with the compensatory information to low-level features simultaneously. MIC is designed to work with LFE in parallel to further improve the information loss resulting from 1 × 1 convolution. Experimental results on MS COCO and UAVDT dataset demonstrate that Dual SIE-FPN achieves competitive performance compared to other state-of-the-art FPNs. In addition, our proposed Dual SIE-FPN can be embedded into any multiscale feature extraction-based computer vision tasks to improve the performance.

This paper presents a novel two-stage amplifier, which cascades a duty-cycled inverter-based OTA and a floating-inverter amplifier (FIA). The proposed OTA-FIA can achieve 72.0dB gain under a 1.2V supply, whose output swing is 420mV. Additionally, it exhibits intrinsic loop stability without compensation and reduces thermal noise during integration. The proposed OTA-FIA is adopted in a low distortion 1-1-1 MASH structure to obtain high resolution. Simulated in a 55 nm CMOS process, the proposed ADC can achieve an SNDR of 94.6dB with a bandwidth of 50kHz. It consumes$363.8\mu \mathrm{W}$from a 1.2V supply at a 5MS/s sampling frequency, resulting in a 176.0dB SNDR-based Schreier FoM.

In this paper, we propose a method to develop optimization for an integrated measurement system of camera and laser sensors based on tensor interpretation. A new metric called vision distance is applied which involves computing Frobenius and Euclidean norms to effectively measure the degree of alignment between two visual entities in 3D space. Using this metric, a performance function is proposed based on the characteristics of the measurement task, and transformed into a convex programming problem to optimize the camera-laser measurement. The primal-dual interior-point method is applied to solve the optimization problem. An experiment is conducted based on the proposed approach for high-accuracy measurement task of two sample objects. The results show the effectiveness of the proposed approach.

In this study, the authors present a novel proof on the maximal rates of space‐time block codes from complex orthogonal design (COD). The method of the proof is derived from an observation about the CODs, which reveals some inherent laws of their structure. The proof is applicable to any CODs, rather than to some specific designs, and does not need any auxiliary matrix or matrix transformation. The conclusion in this study also indicates that the upper bound of the CODs’ rate conjectured by the authors is tight and achievable.

Abstract Summary: Transcription and chromatin regulators, and histone modifications play essential roles in gene expression regulation. We have created CistromeMap as a web server to provide a comprehensive knowledgebase of all of the publicly available ChIP-Seq and DNase-Seq data in mouse and human. We have also manually curated metadata to ensure annotation consistency, and developed a user-friendly display matrix for quick navigation and retrieval of data for specific factors, cells and papers. Finally, we provide users with summary statistics of ChIP-Seq and DNase-Seq studies. Availability: Freely available on the web at http://cistrome.dfci.harvard.edu/pc/ Contact: [email protected]; [email protected]