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Demo Data from EDBT 2026 / reviewers in the wild / expert

Tomás Balderas-Contreras

dblp:43/1243 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 2010
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 67% Hardware accelerators and domain-specific architectures · 33%
Computer networks
1 paper
Cellular and mobile networks · 100%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
block cipher implementation		 0.112005
High performance encryption cores for 3G networks · DAC 2005
Hardware accelerators and domain-specific architectures
cryptographic accelerator		 0.112005
High performance encryption cores for 3G networks · DAC 2005
Reconfigurable computing and FPGAs
FPGA implementation		 0.112005
High performance encryption cores for 3G networks · DAC 2005

Methods — techniques the papers use, named apart from their topics

pipelining · 0.1iterative architecture · 0.1
YearPublicationVenuePosition
2010 A UML 2.0 Profile to Model Block Cipher Algorithms
Tomás Balderas-Contreras, Gustavo Rodriguez-Gomez, René Cumplido
 ECMFA1
2005 High performance encryption cores for 3G networks
abstract
This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the confidentiality and integrity algorithms defined for the Universal Mobile Telecommunication System (UMTS) standard. The first proposal is a pipelined design and the second implements an iterative approach. The throughput for these architectures turn out to be higher than the throughput achieved by other proposals.
Tomás Balderas-Contreras, René Cumplido
 DAC1