Among the various strategies for hiding malicious capabilities in integrated circuits (ICs), analog circuit design techniques have recently drawn increased attention due their lower area, power and delay footprints, which make their detection significantly more challenging. Specifically, switched capacitors have been used for creating stealthy trigger circuits based on toggling activity on a victim wire. Various methodologies for detecting such culprits have been investigated; however, recent literature in this area contains several misconceptions or inaccuracies regarding the topologies of these trigger circuits and the effectiveness of previously proposed detection methods. Therefore, in this paper, we first revisit the design of switched capacitor-based trigger circuits and we present several design configurations which are not encompassed by previously demonstrated models, but which can also serve the same malevolent purpose. We, then, discuss the effectiveness and the shortcomings of existing defense methodologies, and we point towards additional research that is needed in this area.

Unlike the extensive research effort that has been expended over the last 15 years in understanding the threats of hardware Trojans, piracy and counterfeiting of digital Integrated Circuits (ICs), and in developing appropriate prevention and detection solutions, the topic of security and trust remains in a rather nascent state for their analog/radio-frequency (RF) counterparts. Indeed, as shown in a recent survey, which summarized and presented the available body of knowledge in trusted and secure design of analog/RF ICs, our understanding of the pertinent threats and our ability to thwart them through existing solutions are both rather limited. However, given the widespread use of analog functionality (i.e., physical interfaces, sensors, actuators, wireless communications, etc.) in most contemporary systems, comprehending their vulnerabilities and devising pertinent remedies is urgently required. In this paper, we discuss the limitations of the current state-of-the-art in this field, we highlight recent developments, and we suggest research directions and steps to be taken toward designing, fabricating and deploying trusted and secure analog/RF ICs.

Contemporary technology nodes exhibit high defectivity due to complex interactions between the process and certain layout topologies/patterns. Foundries identify such patterns during diagnosis, Scanning Electron Microscope (SEM) inspections, Failure Analysis (FA), etc., and create a database to restrict their presence in future designs. However, such a database can be generated only after fabricating a few products, hence making this process reactive. Ideally, foundries would prefer to have a proactive approach, where such sensitive patterns are available up-front during technology development. Thereby, they can build accurate Hotspot Detection models and offer a robust Product Design Kit (PDK) to even the earliest of customers, either by ensuring that the process is immune to such patterns or by including them in the Design For Manufacturability Guidelines (DFMGs). To enable this, Early Design Space Exploration (EDSE) can be performed, wherein an Electronic Design Automation (EDA) tool generates synthetic layout patterns. In this work, we introduce VIPER, a novel, controlled random walk-based pattern generation method, which not only generates realistic and Design Rule-clean layout patterns, but which also offers versatility so that the generated patterns can be intuitively customized to specific needs. To ensure that the generated patterns are representative of real designs, we data mine designs in previous technology nodes and we learn some of their typical characteristics. Effectiveness of the proposed method is contrasted against the state-of-the-art, commercially available EDA tool.

Information flow tracking (IFT) is a widely used methodology for ensuring data confidentiality in electronic systems and numerous such methods have been developed at various software or hardware description levels. Among them, proof-carrying hardware intellectual property (PCHIP) introduced an IFT methodology for digital hardware designs described in hardware description languages (HDLs). The risk of accidental information leakage, however, is not restricted to the digital domain. Indeed, analog signals originating from sources of sensitive information, such as biometric sensors, as well as analog outputs of a circuit, could carry or leak secrets. Moreover, similar to digital designs, analog circuits can also be contaminated with malicious information leakage channels capable of evading traditional manufacturing test. Compounding the problem, in analog/mixed-signal circuits such information leakage channels can cross the analog/digital or digital/analog interface, making their detection even harder. To this end, in this paper we introduce a PCHIP-based methodology which enables systematic formal evaluation of information flow policies in analog/mixed-signal designs. As we demonstrate, by integrating IFT across the digital and analog domain, our method is able to detect sensitive data leakage from the digital domain to the analog domain and vice versa, without requiring any modification of the current analog/mixed-signal circuit design flow.

Part II of this paper series focuses on automation of the extended proof-carrying hardware intellectual property (PCHIP) framework for data secrecy protection in third-party IPs, which was presented in part I. Specifically, we introduce: 1) VeriCoq-IFT, an automated PCHIP framework for information flow policies and 2) VeriCoq-H, a hierarchy-preserving Verilog-to-Coq converter. VeriCoq-IFT aims to: 1) automate the process of converting designs from an HDL to the Coq formal language; 2) generate security property theorems ensuring compliance with information flow policies; 3) construct proofs for such theorems; and 4) check their validity in a design, with minimal user intervention. VeriCoq-H, on the other hand, seeks to convert the entire functionality of a Verilog design to its Coq representation while preserving design hierarchy. It facilitates the development of hierarchical proofs and enables the construction of hybrid module libraries containing the HDL code and the corresponding reusable lemmas for each module. Applicability of our automated VeriCoq-IFT framework is demonstrated by evaluating trustworthiness of two DES encryption circuits and several genuine and Trojan-infested advanced encryption standard (AES) designs, along with the utility of VeriCoq-H in preventing malicious modification of sensitive data, such as the secret key of an encryption circuit.

Proof-carrying hardware intellectual property (PCHIP) is a previously proposed framework for ensuring trustworthiness of third-party hardware IP through the development of formal proofs for security properties designed to prevent introduction of malicious behavior. Based on this framework, we introduce new approaches for assuring that the secrecy of internal information in a hardware design is not compromised by design flaws or malicious hardware Trojans. Specifically, we devise two PCHIP-based information flow tracking approaches, which enhance the formal PCHIP framework with secrecy tags and/or sensitivity levels in order to provide mechanisms for proving that sensitive information does not reach undesired sites. To assist in the development of data secrecy properties, we also introduce the concept of theorem generation functions, which enable generation of security theorems independent of the target circuit, thereby paving the way for proof automation. In addition, we enhance the PCHIP framework with a hierarchy-preserving methodology and we show its utility in preventing malicious data modification, which may indirectly result in sensitive information leakage, such as by modifying the secret key in a cryptographic core. This enhanced PCHIP framework also enables development of hybrid module libraries, which contain hardware description language code along with proofs of lemmas for these modules. These module libraries can then be used for hierarchically proving security properties in higher level designs, thereby reducing the proof development burden in the general PCHIP framework. Efforts toward automation of the proposed methodologies, as well as evaluation of their effectiveness in identifying design flaws or hardware Trojans in various cryptographic hardware designs are presented in part II of this paper series.

We introduce a machine learning approach for distinguishing between integrated circuits fabricated in a ratified facility and circuits originating from an unknown or undesired source based on parametric measurements. Unlike earlier approaches, which seek to achieve the same objective in a general, design-independent manner, the proposed method leverages the interaction between the idiosyncrasies of the fabrication facility and a specific design, in order to create a customized fab-of-origin membership test for the circuit in question. Effectiveness of the proposed method is demonstrated using two large industrial datasets from a 65nm Texas Instruments RF transceiver manufactured in two different fabrication facilities.

We present our experiences in implementing hardware-based attacks to subvert the results of an election system. The election system was outlined by the Cyber Security Awareness Week (CSAW) Embedded Security Challenge (ESC) competition in 2015, held at the New York University (NYU). The system had multiple layers of security and primarily used homomorphic encryption. The competition presented a challenge to hack the election system such that a preferred candidate wins the election. We cryptanalyzed the given election system to evaluate the effectiveness of various theoretical and practical attacks, and used a custom designed embedded system to demonstrate our attacks. The embedded system was implemented on a Nexys 4 DDR Artix-7 FPGA board. Our work, which earned the first place in the competition, demonstrates that low-cost hardware-based attacks can indeed lead to catastrophic consequences.

Proof carrying hardware intellectual property (PCHIP) introduces a new framework in which a hardware (semiconductor) Intellectual Property (IP) is accompanied by formal proofs of certain security-related properties, ensuring that the acquired IP is trustworthy and free from hardware Trojans. In the PCHIP framework, conversion of the design from a hardware description language (HDL) to a formal representation is an essential step. Towards automating this process, herein we introduce VeriCoq, a converter of designs described in Register Transfer Level (RTL) Verilog to their corresponding representation in the Coq theorem proving language, based on the rules defined in the PCHIP framework. VeriCoq supports most of the synthesizable Verilog constructs and is the first step towards automating the entire framework, in order to simplify adoption of PCHIP by hardware IP developers and consumers and, thereby, increase IP trustworthiness.

By occurring failures in computer networks, routing protocols are triggered to update routing and forwarding tables. Because of invalid tables during update-time, transient loop may occur and packet-drop rate and end- to-end delay increase which means that the quality of service decreases. This paper studies the effect of routing- tables update-time on networks' performability, i.e. the ability of network to deliver services at predefined level. A sample network is studied and the simulation results show that faster updates of routing table, improve network's performability in the presence of failures. Since it may not worth or even be practical to accelerate all routers in the network, this paper suggests finding bottleneck routers and accelerating them in order to improve the performability of the network. The simulation results show that by speeding-up the bottleneck routers of the network, instead of all routers, the desired performability could be achieved.