The fusion of graphene with silicon may provide an effective solution to the problem of scale in electronic devices. This approach will allow the excellent electronic properties of graphene to be combined with known Si device technologies. We review the epitaxial growth of graphene on Si substrates (GOS) for fabricating transistors. GOS has been multifunctionalized by controlling the orientation of the Si substrate. The site-selective epitaxy of GOS has also been developed by controlling the base SiC thin films. These results demonstrate that GOS is suitable for integrated devices.

Self-aligned source/drain (S/D) graphene field-effect transistors (GFETs) with extremely small access lengths were successfully fabricated using a simple device fabrication process without sidewall spacer formation. The self-aligned S/D GFET exhibits superior electrical characteristics, such as the intrinsic carrier mobility of 6100 cm2/Vs, the gate leakage current of 10-10-10-9A and the contact resistance of 412 Ωμm. In particular, a cutoff frequency of 13 GHz was achieved with a rather large gate length (LG= 3 μm), which demonstrates the promising future of this self-aligned GFET.

This paper describes a high-speed GaAs MESFET digital IC design for optical communication systems. We propose novel circuit configurations of a selector and a static delayed flip-flop which are key elements to perform high-speed digital functions. Employing these new design, the selector IC and static decision IC fabricated with 0.12-/spl mu/m GaAs MESFET operated up to 44 Gbit./s and 22 Gbit/s, respectively. These performances are record speed for GaAs MESFETs.

This paper describes a novel delay-error compensation technique using time domain rejlectomtry (TDR) for timing calibration of several-hundred-~llz testers. Here a ramp approximation model is proposed to precisely and simply estimate actual propagation delay times along tester-DUT interfaces. The model is studied by using a newly developed time interval comter module. The experimental results demonstrate that the delay error in TDR can be compensated for within +3 ps. The transmission line model could precisely represent the waveform deterioration caused by capacitive elements and its dependency on the input signal slew rate.

Technologies needed for constructing ULTIMATE, including an 8-ps-resolution timing generator, a formatter with a real-time waveform control function, a 2.5-ps-resolution standard comparator, and a miniaturized 3-GHz 59-pole channel selector are described. Almost all the pin-electronics hardware has been integrated on twelve kinds of LSIs, eight of which are 2.5 K-gate and 400-gate ultrahigh-speed bipolar gate arrays. ULTIMATE realizes +or-55-ps overall timing accuracy by the timing calibration method which combines a standard comparator-based method and a TDR (time-domain reflectometry)-based method.>