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Peter A. Lee

dblp:43/2371 · DBLP profile ↗
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9ranked-venue papers
3as first author
0since 2021 · last 2003
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 5 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 2 · 1 first-authorSystems, architecture and hardware · 1Human-computer interaction and ubiquitous computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Hardware reliability and fault tolerance · 52% Distributed systems · 26% Parallel and multicore computing · 8%
Software engineering, system software, and programming languages
1 paper
Operating systems · 100%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance › error recovery
backward error recovery
0.021996
An Architecture for Tolerating Processor Failures in Shared Memory Multiprocessors · IEEE Trans. Computers 1996
A Model of Recoverability in Multilevel Systems · IEEE Trans. Software Eng. 1978
Distributed systems
fault tolerance
0.021996
An Architecture for Tolerating Processor Failures in Shared Memory Multiprocessors · IEEE Trans. Computers 1996
A Model of Recoverability in Multilevel Systems · IEEE Trans. Software Eng. 1978
Hardware reliability and fault tolerance › processor reliability
processor failure tolerance
0.011996
An Architecture for Tolerating Processor Failures in Shared Memory Multiprocessors · IEEE Trans. Computers 1996
Memory systems
cache coherence
0.011996
An Architecture for Tolerating Processor Failures in Shared Memory Multiprocessors · IEEE Trans. Computers 1996
Parallel and multicore computing › multiprocessor system
shared-memory multiprocessor
0.011996
An Architecture for Tolerating Processor Failures in Shared Memory Multiprocessors · IEEE Trans. Computers 1996
Performance modeling and evaluation
simulation
0.011996
An Architecture for Tolerating Processor Failures in Shared Memory Multiprocessors · IEEE Trans. Computers 1996
Operating systems › fault tolerance
system recovery
0.011978
A Model of Recoverability in Multilevel Systems · IEEE Trans. Software Eng. 1978

Methods — techniques the papers use, named apart from their topics

simulation · 0.0address traces · 0.0backward error recovery · 0.0
YearPublicationVenuePosition
2003 Modeling and Enacting Software Processes Using VRPML
abstract
We evaluate a new visual process modeling language (PML), called the Virtual Reality Process Modeling Language (VRPML). This evaluation utilizes the well-known ISPW-6 benchmark problem as well as the waterfall development model as case studies, and offers comparison with other PMLs where possible. In addition to providing insights into the strengths and limitations of VRPML, this evaluation highlights important lessons learned and offers valuable guidance for the design of next-generation PMLs.
Kamal Zuhairi Zamli, Peter A. Lee
APSEC2
2002 Exploiting a Virtual Environment in a Visual PML
Kamal Zuhairi Zamli, Peter A. Lee
PROFES2
2001 Taxonomy of Process Modeling Languages
abstract
Process modeling languages (PMLs) are languages used to express software process models. Process centered software engineering environments (PSEEs) are the environments used to define, modify, analyze and enact a process model. While both PMLs and PSEEs are important, it is the characteristics of PMLs that are the focus of the article, which leads to a taxonomy different from that presented in other work primarily with the inclusion of important human dimension issues (e.g. awareness support) from computer supported cooperative work (CSCW).
Kamal Zuhairi Zamli, Peter A. Lee
AICCSA2
1998 Programming versus design (poster): teaching first year students
abstract
No abstract available.
Peter A. Lee
ITiCSE1
1996 An Architecture for Tolerating Processor Failures in Shared Memory Multiprocessors
abstract
This paper focuses on the problem of fault tolerance in shared memory multiprocessors, and describes an architecture designed for transparently tolerating processor failures. The Recoverable Shared Memory (RSM) is the novel component of this architecture, providing a hardware supported backward error recovery mechanism which minimizes the propagation of recovery when a processor fails. The RSM permits a shared memory multiprocessor to be constructed using standard caches and cache coherence protocols, and does not require any changes to be made to applications software. The performance of the recovery scheme supported by the RSM is evaluated and compared with other schemes that have been proposed for fault tolerant shared memory multiprocessors. The performance study has been conducted by simulation using address traces collected from real parallel applications.
Michel Banâtre, Alain Gefflaut, Philippe Joubert, Christine Morin, Peter A. Lee
IEEE Trans. Computers5
1993 Object-oriented design: guidelines and techniques
Luiz Fernando Capretz, Peter A. Lee
Inf. Softw. Technol.2
1981 Some Critical Comments on the Paper "An Optimal Approach to Fault Tolerant Software Systems Design" by Gannon and Shapiro
Peter A. Lee, J. L. Lloyd, Santosh K. Shrivastava
IEEE Trans. Software Eng.1
1978 A Reconsideration of the Recovery Block Scheme
abstract
The recovery block scheme has been introduced as a method of providing fault tolerance at the software level in a computing system. From the widespread interest that has been expressed in the scheme there appears to be a standard set of questions which are posed about its implementation and utility. This paper presents a brief overview of the recovery block scheme and then examines in detail the issued that these questions raise.
Peter A. Lee
Comput. J.1
1978 A Model of Recoverability in Multilevel Systems
abstract
Backward error recovery (that is, resetting an erroneous state of a system to a previous error-free state) is an important general technique for recovery from faults in a system, especially those faults which were not foreseen. However, the provision of backward error recovery can be complex, particularly if the implementation of the system is "multilever" and recovery is to be provided at a number of these levels. This paper discusses two distinct categories of multilevel system, and then examines in detail the issues involved in providing backward error recovery in both types of system.
Thomas Anderson 0001, Peter A. Lee, Santosh K. Shrivastava
IEEE Trans. Software Eng.2