Jido is a conversational tactile map and a mobile application prototype to improve the orientation and mobility of visually impaired people. The tactile map can identify the user's touch gestures and their locations during tactile exploration to provide feedback. Users can verbally interact with a conversational agent through their mobile device to receive confirmation, request information of points of interest, and receive step-by-step instructions that can be later reviewed during navigation. In this work, we describe opportunities and challenges faced by tactile map users and present the findings on the preliminary evaluation of our prototype.

There is an increasing concern to improve the accessibility of artworks for blind people. Much of the effort has been focused on helping the visually impaired people to access the exhibition facilities, but the works of art hosted there are still difficult to experience for them. Particularly, the appreciation of visual artworks is hindered as blind visitors are not allowed to touch them in order to conserve their aesthetics and value. In this work we explore our findings using a prototype of a voice interactive multimodal guide designed to improve the accessibility of visual works of arts, such as paintings, for the blind people. The prototype identifies tactile gestures and voice commands that trigger audio descriptions and sounds while a person explores a 2.5D tactile representation of the artwork placed on the top surface of the prototype. Our preliminary findings include the results of eight user tests and Likert-type surveys.

The development of 3D printing technology has improved the engagement of the visually impaired people when experiencing two-dimensional visual artworks. However, it is still difficult to explore, experience and get a clear understanding. We introduce an interactive multimodal guide in which a 3D printed 2.5D representation of a painting can be explored by touch. Touching determined features in the representation triggers localized verbal, audio, wind, and light/heat feedback events that convey spatial and semantic information. In this work we present a working prototype developed through three sessions using a participatory design approach.

We present D-TOX, a user-centered design that by applying gamification to a smart lamp and mobile application reduces the frequency of smartphone usage during nighttime. Many children make use of their smartphone without any significant reason before sleep which prevents them from getting a good rest. To avoid this, we focused on developing a corrective system that removes their smartphone from their hands. We reward the user using gamification. The lamp's color and intensity varies depending on the smartphone usage which feedbacks the user. Through a user study, we confirmed the significance and usability of the device.

The development of the information technologies has benefited education through the integration of technologies and didactic tools to ease and enhance the education experience in and outside of the classroom. After a survey in several welfare centers, it was revealed that the visually impaired community has yet to benefit from the technology integration. In this work, we introduce Slate Master, a mobile device didactic tool for the visually impaired designed to ease learning how to use the Braille slate. The Braille slate is a tool used by the visually impaired to manually write Braille encoded text on paper. Slate Master is composed by a Braille tutor mobile application and a custom input interface that mimics the use of the Braille slate. We also present the insights obtained from a preliminary study performed with six Braille education experts that led to the design and development of Slate Master.

As the number of dual-income household's increases, time spent by parents with children has been decreasing. To solve this issue, we have designed our system, Fam-On Platform. This platform is intended that it has increased the quantity of time by making parents recognized the lack of parenting time through time measurement. On the other hands, showing the amount of parenting time, it tries to decrease the imbalance of parenting time between fathers and mother as well. In this process, we manufactured physical wearable watch devices to promote children's interest and provide direct feedback to the family. Also, we tried to improve family bond by family-sharing time, providing contents to share among family members through application including gamification elements. We have completed a prototype of our platform and conducted pilot test targeting one child. We could gain the results we intended and find issues we need to improve further.

Playful learning is a powerful method to enhance children's engagement with teaching material, often resulting in better learning. Several prior works demonstrated the existence of a relation between tangibles and engagement, but they did not characterize it with specific measures. Therefore, this paper aims to describe the degree of engagement with tangible blocks by quantifying children's proactive and passive actions during a learning session. Based on a user study with 36 kindergarten children, our findings show that tangibles support a higher degree of engagement, fosters attention and collaboration, and possibly lead to more active learning.

In this paper, we present an interactive and connected tableware system for promoting children to eat vegetables more. Our system aims to encourage children to eat vegetables more and educate them to understand the benefits of those vegetables. Our system comprises a food tray, a spoon and a smartphone cradle, which named "Healthy Tray", "Healthy Spoon" and "Healthy Cradle" respectively. We also present a mobile application with education and gamification elements connected to our tableware. Healthy Cradle is particularly designed to enhance the interaction and communication between children and their parents while playing the game.

In this paper we present DenTeach, a smart brush with a doll-shaped tangible device. We designed and to foster children's good tooth brushing habits by explicitly showing the effect of their tooth brushing on the teeth of a physical avatar in real time. A pilot study conducted with 15 children (ages between 6 and 12) shows that there was possibly positive change of their attitudes to tooth brushing and motivations for tooth brushing when they brushed their teeth with DenTeach. As future work, we plan to develop a smartphone app that interacts with DenTeach so that the children users can constantly check their tooth brushing habits with more fun.

Spatial ability is one of mental ability which grounds children's educational development critically, and is used in whole dimensions of our life in conjunction with STEM (Science, Technology, Engineering, and Mathematics) learning. In this paper, we present a gamification tool socalled "Hide and Seek" which nourishes spatial ability. A child seeks a place where a tagger is hidden by comparing Lego village and the corresponding picture taken by the tagger. A concept of this game is comparing the 2-dimensional flat surface of the picture and 3-dimensional Lego village. We conducted user tests of Hide and Seek with children. The aims of user test are observing usability, usage of spatial language and game elements while children are playing the game. From the test, we observed spatial cognition factor and dialogues used during problem solving and usability. Based on the results, we also derived additional concept refinements of the presented educational game system.

This study aims to design socially assistive robotics (SAR) that provide assistance to children aged 4-6 years; this is achieved through machine learning of languages, and by evaluating changes in children's reactions according to language learning stages of a robot. To this end, an assistive toy for language learning, named ARA, was developed and taught the language spoken by children who played with Furby and the responses and reactions of children during the different language learning degrees of ARA were video-recorded and analyzed. The recorded videos were quantitatively analyzed from a behavioral perspective (i.e. talking to Furby, touching or stroking Furby, and talking to his/her mother) and emotional perspective (i.e. positive expression, neutral expression, and negative expression). The analytical results were compared according to the language learning stages of ARA. Furthermore, on the basis of the analysis, it was evident that if robots can naturally communicate with children through gradual language learning based on conversations with the children, the children can improve their conversational ability as well as their communication skills by playing with robots. In addition, the children can interact with a communication target more positively compared with their reaction to simple movements or sound of a robot, and this can help achieve more positive emotional development in children.

In this paper we investigate how people emotionally respond to the emotional expression of a plant when external stimuli were given to the plant. For this purpose we built a simple LED emoticon-based device as an emotional proxy for delivering inner states of a plant, assuming the inner states of a plant can be changed depending on either positive or negative external stimuli. Our pilot study suggests that people's attitude on plants can be influenced by observing the emotional expressions of a plant.

Incorrect postures and long sitting sessions are among the main causes of back pain and discomfort, a problem affecting a growing portion of office workers. In the past, researchers have suggested possible ways to notify with alerts those users who sit improperly, but often such notifications are perceived as intrusive and tend to be ignored. In this paper, we present a flower-shaped physical avatar that subtly and pleasantly (through motion, colors and sounds) provides an ambient feedback to users about their postures. Compared with similar previous work, the flower-avatar described in this paper presents, through better sensing and fine-grain output capabilities, a more expressive ambient media platform that showcases the potential of media ambient avatars in health-care scenarios.

In this paper, an area efficient VLSI architecture of decision feedback equalizer is derived accommodating 64/256 QAM modulators. This architecture is implemented efficiently in reusable VLSI structure using EDA tool due to its regular structure. The main idea is to employ a time-multiplexed design scheme grouping the adjacent filter taps with correlated internal dataflow and with data transfer having same processing sequence between blocks. We simulated the proposed design scheme using SYNOPSYSTM and SPWTM. Index Terms - Decision feedback equalizer, QAM, reusable VLSI implementation, FIR filter.

This paper presents a new VLSI architecture of the Motion Estimation in MPEG-2. Previously, a number of full search block matching algorithms (BMA) and architectures using systolic array have been proposed for motion estimation. However, the architectures have an inefficiently large number of external memory access. Recently, to reduce the number of accesses in one search block, a block matching method within a search area to reuse the search data is provided using systolic process arrays. To further reduce the data access and computation time during the block matching, we propose a new approach through the reuse of the previously-search data in two dimensions. Our new architecture in this paper is an extension from our previous work such that we reuse the previously searches area not only between two consecutive columns but also between two consecutive rows, so as to entirely remove redundant memory access. Experimental results show the efficiency of our algorithm.

We propose a new global routing area estimation approach for high-performance very large scale integration and multichip modules (MCMs). The objective is to route nets with minimum density of global cells, producing a four-bend routing for each two-terminal net. We propose an approximate upper bound on global cell d/sub H//spl les/2d/sub 0/log(m/(2d/sub 0/)), in an m/spl times/m two-dimensional array, where d/sub 0/ is the estimated lower-bound density. The total wirelength is (2/spl alpha/+/spl beta/)4m/sup 2/d/sub 0//3, where /spl alpha/+/spl beta/=1 and /spl alpha/ is the percentage of diagonal combinations and /spl beta/ is the percentage of adjacent combinations of nets. If /spl alpha//spl les//spl beta/ (this assumption holds since a good placement minimizes the longer wires), then the total wirelength is at most 2m/sup 2/d/sub 0/. By counting on the adjacent and diagonal combinations separately in the cost function, d/sub R//spl les/[4d/sub 0//3]/spl times/log([m/(4d/sub 0//3)]). We verified that the bound obtained are realistic in the worst case. A solution to this problem can be used for quick estimation of necessary wiring space (for standard cell array designs) and difficulty of routing (for gate array designs) in the early design planning stage.

In this paper, we introduce a high-speed and low power Phase-Frequency Detector (PFD) that is designed using modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop. This PFD has a simpler structure with using only 19 transistors. The operation range of this PFD is over 1.2 GHz without additional prescaler circuits. Furthermore, the PFD has a dead zone less than 0.01 ns in the phase characteristics and has low phase sensitivity errors. The phase and frequency error detection range is not limited as in the case of the pt-type and nc-type PFDs. Also, the PFD is independent from the duty cycle of input signals. A new charge-pump circuit is presented that is designed using a charge-amplifier. A stand-by current enhances the speed of charge-pump and removes the charge-sharing which causes a phase noise in the charge-pump PLL. Also, the effects of clock feed-through are reduced by separating the output stage from UP and down signal. The simulation results base on a third-order PLL are presented to verify the lock-in process with the proposed PFD and charge-pump circuits. The PFD and charge-pump circuits are designed using 0.8 /spl mu/m CMOS technology with 5 V supply voltage.

There are a number of VLSI problems that have a common structure. We investigate such a structure that leads to a unified approach for three independent VLSI layout problems: partitioning, placement, and via minimization. Along the line, we first propose a linear-time approximation algorithm on maxcut and two closely related problems: k-coloring and maximal k-color ordering problem. The k-coloring is a generalization of the maxcut and the maximal k-color ordering is a generalization of the k-coloring. For a graph G with e edges and n vertices, our maxcut approximation algorithm runs in O(e+n) sequential time yielding a nodebalanced maxcut with size at least (w(E)+w(E)/n)/2, improving the time complexity of O(e log e) known before. Building on the proposed maxcut technique and employing a height-balanced binary decomposition, we devise an O((e+n)log k) time algorithm for the k-coloring problem which always finds a k-partition of vertices such that the number of bad (or "defected") edges does not exceed (w(E)/k)((n-1)/n)/sup log k/, thus improving both the time complexity O(enk) and the bound e/k known before. The other related problem is the maximal k-color ordering problem that has been an open problem. We show the problem is NP-complete, then present an approximation algorithm building on our k-coloring structure. A performance bound on maximal k-color ordering cost, 2kw(E)/3 is attained in O(ek) time. The solution quality of this algorithm is also tested experimentally and found to be effective.

We propose a new global net distribution approach for high-performance m/spl times/m two-dimensional arrays of very large scale integration and multichip-modules. The objective is to route n nets with minimum density of global cells, using a "small" number of bends. There are a number of applications where it is necessary to limit the number of bends on each wire. For example, it is desirable to limit the number of bends on each microstrip (transmission) line, for mismatches of line impedance can cause reflections from the junction points such as bends and vias. Furthermore, for high-performance routing, intersections of wires cause the use of more vias, which in turn require the use of more routing resources (because of the larger via pitch). This is the first paper that addresses a graph-theoretic framework to solve the bend-constrained global routing problem in two-dimensional arrays. In this paper, at each level of an underlying quad-tree, we present a novel four-bend routing algorithm by decomposing the original problem at level i into two subproblems that can be solved exactly based on a two-stage approach of smaller-sized linear program followed by min-cost flow networks. The overall (i.e., entire level of the four-way partition hierarchy) constraint and variable size for the first stage is O(md/sub o/), while the overall run time for the second stage is O(n/sup 3/ log n/sup 2/). The time complexity of such a hierarchical approach is one order of magnitude less than one of constructing a global routing using the min-cost-flow-based flat design approach. Last, we present an extension that permits a limited degree of control over the number of bends. The proposed algorithm can also be used for estimating the wireability in the early design planning stage for high-level synthesis. Experimental results showed the effectiveness of the proposed algorithm.

Given a signal net N = s, 1, a*-, n to be the set of nodes, with s the source and the remaining nodes sinks, an MRDPT ( minimum-cost rectilinear Steiner distance-preserving tree) has the property that the length of every source to sink path is equal to the rectilinear distance between the source and sink. The minimum-cost rectilinear Steiner distance-preserving tree minimizes the total wire length while maintaining minimal source to sink length. Recently, some heuristic algorithms have been proposed for the problem of finding the MRDPT. In this paper, we investigate an optimal structure on the MRDPT and present a theoretical breakthrough which shows that the mm-cost flow formulation leads to an efficient O(n^4 log n) time algorithm. A more practical extension is also investigated along with interesting open problems.

We propose a new approach for optimizing clock trees, especially for high-speed circuits. Our approach provides a useful guideline to a designer, by user-specified parameters, and three of these tradeoffs are provided in this paper. (1) First, to provide a "good" tradeoff between skew and wire length, a new clock tree routing scheme is proposed. The technique is based on a combination of hierarchical bottom-up geometric matching and minimum rectilinear Steiner tree. Our experiments complement the theoretical results. (2) For high-speed clock distribution in the transmission line mode (e.g., multichip modules) where interconnection delay dominates the clock delay, buffer congestion might exist in a layout. Using many buffers in a small wiring area results in substantial interline crosstalks as well as wirability, when the elongation of the imbalanced subtrees is necessary. Placing buffers evenly (locally or globally) over the plane at the minimum impact on wire length increase helps avoid buffer congestion and results in less crosstalk between clock wires. Thus, an effective technique for buffer distribution is proposed. Experimental results verify the effectiveness of the proposed algorithms. (3) Finally, a postprocessing step constraining on phase-delay is also proposed. The technique is based on a combination of hierarchical bottom-up geometric matching and bounded radius minimum spanning tree. The proposed algorithm has an important application in MCM clock net synthesis as well as VLSI clock net synthesis.>

Article A buffer distribution algorithm for high-speed clock routing Share on Authors: Jun Dong Cho View Profile , Majid Sarrafzadeh View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 537–543https://doi.org/10.1145/157485.165019Published:01 July 1993 18citation291DownloadsMetricsTotal Citations18Total Downloads291Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access