The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful defense against burst data errors, the significant circuit area and power consumption of customized RS decoder hardware can be limiting for embedded computing environments. To support enhanced performance decoding with minimal power consumption, a dynamically-reconfigurable FPGA-based Reed-Solomon decoder has been developed. Our errors-and-erasures decoding system uses multiple erasure blocks to identify the location of likely corrupted data and multiple decoders to attempt error correction. The RS decoder design is implemented in reconfigurable hardware to leverage architectural parallelism and specialization. Run-time dynamic reconfiguration of the decoding system is used in response to variations in channel conditions to support the fastest possible data rate while, as a secondary metric, minimizing decoder power consumption. Algorithm parameters for the decoding system have been determined via simulation and the design has been implemented in Altera Stratix FPGAs. Through experimentation using an Altera 1S40 Stratix FPGA, we show that dynamic reconfiguration can result in an 14% performance improvement versus a non-reconfigurable decoder implementation. Comparisons with a Pentium IV microprocessor illustrate five orders of magnitude performance improvement.

The interactive learning environment (ILE) is designed to combine the traditional resources of a textbook with the "hands-on" design experiences that are vital to a real understanding of basic engineering principles. The ILE builds on the technology developed for the World Wide Web to provide a learning environment that can be easily accessed from any browser. In addition to browseable text, Java-based computer-aided design (CAD) tools can be accessed through interactive figures embedded in the text, where students can investigate circuit behavior under the guidance of focused tutorials.

We address the problem of automatically verifying large digital designs at the logic level, against high-level specifications. We present a technique which allows for the verification of a specific class of systems, namely systems with synchronous globally timed control. To a first approximation, these are systems where a single controller directs the data through the data path and decides (globally) when to move the data. We address the verification of these systems against a Signal Flow Graph (SFG) specification, or a specification in an applicative language such as SILAGE. In this paper, a method is presented for verifying the implementation against an intermediate SFG, which is an expansion of the original specification in such a way that all the operations correspond to Register Transfers (RT's) in the implementation. In this SFG, complex arithmetic operations such as multiplications may have been decomposed into simpler ones, such as shifts and additions, and new operations may have been introduced for maintaining iteration indices and computing addresses of memory locations. SFG's can be viewed as maximally parallel synchronous machines. Both the implementation and the specification are then Finite State Machines, having string functions (input/output mappings) associated with them. Correctness is taken to mean that a certain relation (the /spl beta/-relation) holds between these string functions.>

A method is presented for mapping conditional affine resources equations (CAREs) into systolic-type architectures. The tasks of localization and of space-time reindexing are formulated as a single branch and broad search problem. The combined formulation allows these problems to be solved concurrently and thus ensures that true optimal solutions are derived. The employed space-time reindexing method applies different affine transforms to different array variables. The employed space-time reindexing method applies different affine transforms to different array variables. Multistage localization is effected by a search-based technique which exploits specific characteristics of the combined formulation. The search procedure comprehensively explores the space of designs defined by the constraints of these methods. For a given input, all legal designs which optimize a delay-based objective function are generated. The method has been implemented as part of the array synthesis system DESCARTES. Example problems are presented to demonstrate the feasibility of the technique.>

Uses string function theory to develop an efficient methodology for the verification of logic implementations against behavioral specifications. First, the authors define five primitive relations between string functions, other than strict automata equivalence, namely: don't care times, parallelism, encoding, input don't care and output don't care relations. These relations have attributes, For instance, the parallelism relation has an attribute corresponding to the degree of parallelism. For each of these primitive relations, the authors derive transformations on the specification and the implementation such that the relation holds between the specification and implementation if and only if the transformed circuits exhibit the same input/output behavior. This reduces the problem of verifying primitive relations to automata equivalence checking. They enlarge the set of relations between specifications and implementations by including arbitrary compositions of the five primitive relations. To reduce the cost of verifying such a composite relation, the authors show that, given an arbitrary composite relation, a fixed order composite relation can be constructed under certain assumptions), where the primitive relations occur at most once in a predetermined order, such that the original relation holds between two machines if and only if the fixed order relation holds. For the fixed order composite relation, they derive again transformations on the specification and the implementation which reduce verifying the composite relation to performing one equivalence check. The end result is a sound and complete proof method for proving arbitrary compositions of relations by transforming the specification and the implementation and performing an equivalence check on the transformed finite state machines.>

A general strategy for automatically generating and verifying sufficient correctness properties for a broad class of synchronous processors is presented. Given a particular specification and implementation pair, it is shown how basic correctness properties can be algorithmically translated into a set of computation tree logic (CTL) formulae which are sufficient for equivalence between the behavioral and logic descriptions. Preliminary experimental results on the verification of microcoded and array processors are presented.>

A framework for VLSI design databases which supports fine-grained incremental consistency maintenance between different views of a design is presented. The framework provides for structural views of a design such as logic or circuit schematic, symbolic layout, and physical layout, and supports representation of geometric design rule constraints between design objects. A prototype interactive design system which provides a user interface to three structural view types (gate and circuit schematics, and symbolic layouts) is presented. Features of the prototype system are automatic propagation of incremental operations between views and high-speed online generation and evaluation of geometric design rule constraints.>

The problem of implementation verification at the behavioral level is addressed. A formalism is needed for specifying synchronous circuits and expressing correctness requirements that leave room for modifying the input/output behavior of the implementation. Furthermore, a procedure is needed to verify these requirements. The authors model both specifications and implementations as synchronous logic circuits, and cast the correctness requirements as relations between string functions associated with a specification and an implementation. They define six primitive relations between string functions, namely delay, don't care times, parallelism, encoding, input don't care, and output don't care relations. These relations have attributes, for instance, a delay time for the delay relation. It is shown that these relations can be verified by transforming the specification and the implementation and performing an input/output equivalence check. The authors also allow for composite relations, and show that, given an arbitrary composite relation, a closely related composition can be constructed which can be verified through one equivalence check. Experimental results are presented.>

This paper describes a circuit analysis program aimed at quickly solving linear interconnection circuits with inductance and coupling. It computes circuit responses to varying degrees of detail, varying from a simple Elmore delay to a good waveform estimate. Allowable circuit forms are much more flexible than for existing Elmore delay algorithms. Large networks or distributed lines can be reduced to a form of transfer function that can subsequently be analyzed much more efficiently with the waveform moment methods.

The two tasks involved in the design of VLSI systems, synthesizing the circuit and then analyzing it to verify the desired behavior and performance, are becoming intertwined, and performance constraints are being used to drive synthesis. This approach requires the ability to explore efficiently many design options and to find global optima over the several consistently aligned representation levels simultaneously. General requirements for performance-directed synthesis are characterized, followed by an overview of algorithms used for performance optimizations both within and between the several levels of representation. The need for techniques for simultaneous constraint optimization and a perspicuous characterization of the total design space is highlighted.>

The process of verifying that a circuit's schematic netlist obeys a particular design methodology is formalized. Circuit correctness is tied to a rigorous set of context free grammar composition rules. These rules define how a small set of module symbols may be combined for circuits adhering to the design methodology. Schematic netlists are represented as graphs, and composition rules are defined as graph transformations akin to grammatical productions. Starting with a circuit netlist, a hierarchical parse tree that can demonstrate the wellformedness of the circuit is constructed. The procedure is hierarchical, incremental, and fast. GRASP operates one to two orders of magnitude faster than previous approaches.

The authors present experimental results demonstrating the effectiveness of waveform relaxation (WR) for solving the large, sparsely connected algebraic and differential system generated by standard spatial discretization of the two-dimensional time-dependent semiconductor device equation. The experiments demonstrate that WR converges in a uniform manner, and that there is typically some multirate behavior in a device that the WR algorithm can exploit. Speed and accuracy comparisons are made between standard direct methods, red/black Gauss-Seidel WR, and red/black overrelaxed WR. For their experiments, calculated terminal currents matched well between the methods, and overrelaxed WR was up to a factor of 3 faster than direct methods.>

The authors report a quantitative comparison of area evaluation metrics for CMOS transistor placement, along with a novel analysis technique to determine their absolute merit. The transistor placer TOPOLOGIZER was used to generate test case placements. The resolution of transistor placement algorithms based on metrics (e.g. simulated annealing, branch and bound) are limited to the resolution of the metric. The best metric studied was only able to correctly identify, with 90% accuracy, the better of two placements whose layout areas differed by more than 30%.>

A macromodeling and timing simulation technique is presented that allows fast and accurate delay calculations for CMOS circuits. This method is well suited for delay calculations of regular structure VLSI circuits, as well as circuits designed from standard cell libraries. Timing models for both logic gate and transmission gate circuit forms are developed. Typical delay times were within 5% for logic gate circuits and 10% for transmission gate circuits when compared with SPICE results. The execution time of experimental simulator was over two orders of magnitude faster than SPICE.>

This paper presents a graph-theoretic compactor that minimizes the areas of the bounding rectangle and the individual rectangles in the layout. The minimization problem is formulated as a two-stage process. In the first stage, the area of the bounding rectangle is minimized, and in the second stage, the weighted sum of the areas of the individual rectangles is minimized, which automatically minimizes the lengths of the inter-connecting wires. This approach provides a general and rigorous method for wire-length minimization. Algorithms for generating and solving the constraint graph are proposed. The minimization algorithm includes a graph-theoretic Simplex method that can be used to solve minimization problems whose constraints can be expressed in terms of a directed graph.

This paper investigates technical issues concerning the automated generation of highly regular VLSI circuit layouts (e.g. RAMs, PLAs, systolic arrays) that are crucial to the designability and realizability of large VLSI systems. The key is to determine the most profitable level of abstraction for the designer, which is accomplished by the introduction of macro abstraction, interface inheritance, delayed binding, and the complete decoupling of procedural and graphical design information. These abstraction mechanisms are implemented in the Regular Structure Generator, an operational layout generator with significant advantages over first generation layout tools. Its advantages are demonstrated by a pipelined array multiplier layout example.

The throughput of a combinational array multiplier is shown to be asymptotically suboptimal using performance measures derived from VLSI models of computation. Applying a systematic transformation called retiming, a class of asymptotically optimal pipelined array multipliers is obtained. The optimum circuit performance within this class must be deternmined empirically through repeated iterations of multiplier layout generation, circuit extraction, and electrical simulation. The structure of these pipelined multipliers facilitates such an empirical investigation by admitting very regular layouts that can be generated quickly and interactively.

In this paper, a comprehensive overview of Computer Architecture for Digital Signal Processing is given. Such architectures are seen as the result of constraining influences from the nature of digital signal processing algorithms, architectural techniques including appropriate choice of primitive elements, the underlying digital system technology, and programming languages for digital signal processing. Following a consideration of these influences, several examples are given ranging from chips through board level processors, to attached support processors with very high throughput. Trends for the future are discussed throughout the paper.

Provides an overview of the technical articles and features presented in this issue.

A perspective is developed of the requirements for and the design of high-performance speech processing systems. These are viewed as complex systems composed of two hierarchies including a structural hierarchy of various sized units and an additional hierarchy of qualitatively distinct constraint domains. The nature of these constraints and their interaction is characterized, as well as the criteria for choice of units in the structural hierarchy. The unbounded set of surface phenomena that must be related to these units is shown to be represented by a range of patterns based on equivalence classes derived from the functional contrasts that must be maintained by the symbolic unit values. These abstract classes are related to surface correlates by complicated integrative processes, the nature of which has only recently been studied. Finally, the influence of computer science, which can be regarded as the study of complex systems, is described and the requirements for aggressive research facilities needed for further progress are developed.

Article Free Access Share on Reflections on twenty years of the ACL Author: Jonathan Allen Massachusetts Institute of Technology, Cambridge, MA Massachusetts Institute of Technology, Cambridge, MAView Profile Authors Info & Claims ACL '82: Proceedings of the 20th annual meeting on Association for Computational LinguisticsJune 1982 Pages 104–106https://doi.org/10.3115/981251.981281Online:16 June 1982Publication History 0citation132DownloadsMetricsTotal Citations0Total Downloads132Last 12 Months55Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

This paper describes the architectural transformation undergone by a digital signal processor developed at MIT as it was adapted from a TTL MSI implementation to a monolithic MOS implementation. Though the choice of architectures in each technology was guided by the functional requirements of the Klatt vocal tract model (16-pole, 2-zero formant synthesis), the resultant architectures were dramatically different. The example demonstrates that good TTL architectures may not translate neatly into good MOS architectures and that, if a system in the first technology is to be reproduced in the second, a moderate investment in architectural redesign may yield great returns during the steps of circuit design, layout and testing. In fact, this case shows that as an architecture grows progressively simpler, it can also grow progressively more general-capable of serving a broader class of applications than first intended.

The goal of design automation for VLSI is to provide tools which permit rapid, correct, and economical design of custom circuits subject to constraints of area, time, or power. This design process can be seen as the transformation of a given input specification (e.g. a formal representation of an algorithm) through a succession of representations (architecture, functional elements, gates, circuits, layout) until a mask specification is obtained which can then be interpreted by a fabrication process to yield correctly working physical circuits. The major problems faced, then, are the selection of these representations together with the means to create, modify and transform them. Hovering over these needs is the growing cloud of complexity, which demands organized systems design such that the resulting specification can be easily understood, changed, and extended along with other designs to form still larger circuits. One term that ties all of these requirements together is productivity, and IC design is currently facing all the problems encountered in software system design. Just as programmers produce very few debugged instructions per day, today's IC designers usually produce less than ten “debugged transistors” per day when creating new logic circuits.

In recent years,a great deal of evidence has been collected which gives substantially increased insight into the nature of human speech perception.It is the author's belief that such data can be effectively used to infer much of the structure of a practical speech recognition system.This paper details a new view of the role of structural constraints within the several structural domains (e.g.articulation, phonetics, phonology, syntax, semantics) that must be utilized to infer the desired percept.

From these studies, it is possible to model the fundamental frequency (F0) contours for sentences which exhibit a comprehensive range of linguistic communicative functions, and thus extend the understanding of the role of F0from simple declarative sentences to a class which more nearly typifies the utterances found in nornsl discourse. Any attempt to characterize discourse-length utterances must account for these factors, and it is felt that the use of language functions within a speech act framework provides an insightful means to account for these F0phenomena.

In this subject, we treat computer structure as an element of a group of interacting structures including the technology, algorithm, data, and programming language. In the belief that the best designs result when these structural factors “match” in a complementary manner, the influence of each of these domains is carefully studied at both the conceptual and descriptive levels. Thus a modular treatment of current technology is provided, as well as a thorough analysis of algorithmic structure as reflected in computational schemata. Single-sequence machine design is discussed, including advanced topics such as multiple functional unit conflict resolution. Following a presentation of microprogramming and input/output, virtual ideas centered around the notion of process are introduced, leading to the design of multiprocessing and multiprocessor systems. These ideas are applied and extended in the presentation of the Burroughs B6700 as a higher-level language machine designed to execute ALGOL efficiently. Finally, the subject concludes with an introduction to general interpretive structures for high-level languages.