A cryogenic complementary metal-oxide semiconductor (cryo-CMOS) ultra-high-frequency (UHF) analog filter designed for enabling scalable quantum control interfaces is presented in this work. Effective filtering at both analog-to-digital and digital-to-analog conversion stages is critical to maintain signal integrity and achieve high-fidelity qubit control and readout. The proposed filter employs a differential flipped-voltage-follower-based topology, facilitating compact single-branch design, high linearity, and low power consumption. An on-chip buffer stage and a de-embedding technique for precise chip measurements are also presented. The filter is designed using the GlobalFoundries 22nm fully depleted silicon-on-insulator (FD-SOI) technology, leveraging a low-voltage operation of 0.8 V, facilitating low power consumption. A key advantage of using FD-SOI technology for enabling cryogenic quantum computing hardware is the additional degree of freedom provided by the available back-gate transistor connection through which the – increased by the cryogenic (4 K) environment – threshold voltage can be restored. The filter's performance is validated through post-layout simulations, demonstrating improved performance compared to the state-of-the-art literature regarding bandwidth, linearity, and power consumption.

This brief presents a new method to characterize the linearity of on-chip filters with accurate characterization of the filter’s transfer function (TF) in both its bandpass and stopband. Unlike conventional methods, this approach uses only one buffer, simplifying the design and improving accuracy. The filter and buffer are designed using GlobalFoundries (GF) 22-nm FDX technology, incorporating a back-gate biasing tuning mechanism in the buffer design that aims to maintain the performance of the buffer under process variation. The postlayout simulations demonstrate that the new method achieves a filter linearity of$\text {IIP3}=10.46~\text {dBm}$, with an accuracy of 99.4% compared to the standalone filter’s linearity. Similar consistency is observed across process corners.

We present a hybrid phase-detection based switching controller incorporating a look-up table (LUT) based finite state machine (FSM). This FSM can help in improving the settling response in fractional-N digital phase-locked loops (DPLLs). The settling time of the DPLL is further improved by using a grey counter-based coarse time-to-digital converter (TDC), which avoids metastability issues arising in binary counter-based TDC. A 2.7-5.5 GHz gear-shift mechanism based ring-oscillator fractional-N DPLL (FNDPLL) has been implemented in the CMOS 65-nm LL technology. The MATLAB and cadence simulation results of the FNDPLL show that the system with the reference clock ($F_{r\mathrm{e}f}$) of 100MHz can achieve a worst-case settling time of 3$\mu$s over an octave tuning range with 28 mW of power consumption.

The enhancement in the settling response of frequency synthesizers would open up prospects for new applications such as spread spectra and frequency hopping systems. Toward deriving a methodology for a fast settling response, we present a switched-loop digital phase locked loop (DPLL) incorporating an integral-derivative controller-based subsystem. The dominant features accelerating the settling response with low jitters in this DPLL are: 1) hybrid phase detection with a state machine using differential and double integration filtering effect and 2) a time-interleaved direct digital synthesizer (DDS)-based digital-to-time converter (DTC) with stable-edge sampling. A 5-GHz fractional-N DPLL (FNDPLL) has been implemented in CMOS 65-nm-LL technology with the proposed technique of loop-order switching. The measured results of the implemented FNDPLL highlight that the system is capable of fastest reported frequency settling to ±25-ppm error within 1.5 μs, using a reference clock frequency of 100 MHz. With one-time calibration, the downsampled output of DDS array-based phase interpolator achieves an integral nonlinearity (INL) of 0.25 ps, as a fractional divider in the loop.