Event-based encoding reduces the amount of generated data while keeping relevant information in the measured magnitude. While this encoding is mostly associated with spiking neuromorphic systems, it can be used in a broad spectrum of tasks. The extension of event-based data representation to other sensors would provide advantages related to bandwidth reduction, lower computing requirements, increased processing speed and data processing. This work describes two event-based encoding procedures (magnitude-event and rate-event) for two sensors widely used in industry, especially for navigation in mobile systems: digital magnetic compass and ultrasonic distance sensor. Encoded data meet Address Event Representation (AER) format for further transmission, processing and visualization. Two encoding procedures and their associated AER conversion from sensor data are described, using an AVR microprocontroller to perform the task in real-time. Results are transmitted to a computer via USART, displayed and recorded using Matlab or jAER visualization tool. A comparison with classic transmitting and processing of sensor data is done to evaluate the convenience of the proposed encoding. Results show that data transmission bandwith can be reduced up to 95% under certain conditions, envisaging that pure or mixed regular/event-based data sensors are desirable for high speed transmission and low computer processing while keeping relevant information, which is highly desirable for mobile systems.

With growing demands in real-time control, classification or prediction, algorithms become more complex while low power and small size devices are required. Matrix multiplication (direct or transpose) is common for such computation algorithms. In numerous algorithms, it is also required to perform matrix multiplication repeatedly, where the result of a multiplication is further multiplied again. This work describes a versatile computation procedure and architecture: one of the matrices is stored in internal memory in its circulant form, then, a sequence of direct or transpose multiplications can be performed without timing penalty. The architecture proposes a RAM-ALU block for each matrix column, being connected in a systolic ring. The computation is propagated through internal RAM-ALU blocks. The architecture exploits local connections, minimizing delays. The system is described as an IP core, it is fully parameterisable to customize matrix size and data format when implementing. An$N\times N$matrix multiplication is performed in$\mathcal{O}(N^2)$clock cycles requiring$N$RAM-ALU blocks being$2N$in memory size. For a Virtex7 FPGA, clock runs at 340 MHz for 100$\times$100 and 290 MHz for 1000$\times$1,000 matrix size with 1 clock cycle per element multiplication.

Typically, hardware implemented neural networks are trained before implementation. Extreme learning machine (ELM) is a noniterative training method for single-layer feed-forward (SLFF) neural networks well suited for hardware implementation. It provides fixed-time learning and simplifies retraining of a neural network once implemented, which is very important in applications demanding on-chip training. This study proposes the data flow of a software support tool in the design process of a hardware implementation of on-chip ELM learning for SLFF neural networks. The software tool allows the user to obtain the optimal definition of functional and hardware parameters for any application, and enables the user to interact throughout the design process. Combining in a transparent way for the user, simulation and Xilinx synthesis tools, the tool recommends the optimal configuration, generating, finally, a synthesizable IP-core. As application, the field-programmable gate array implementation for real-time detection of brain areas in electrode positioning during a deep brain stimulation surgery is described. The generated IP-core can execute a peak of 95 ELM trainings per second on a low-cost Spartan 6 device, making possible its real-time use in this application.

Extreme Learning Machine (ELM) is a noniterative training method suited for Single Layer Feed Forward Neural Networks (SLFF-NN). Typically, a hardware neural network is trained before implementation in order to avoid additional on-chip occupation, delay and performance degradation. However, ELM provides fixed-time learning capability and simplifies the process of re-training a neural network once implemented in hardware. This is an important issue in many applications where input data are continuously changing and a new training process must be launched very often, providing self-adaptation. This work describes a general SLFF-NN design environment to assist in the definition of neural network hardware implementation parameters including real-time ELM training. The software design environment uses initial user-provided input data with information about the type of problem: sample dataset and validated results, input fields, accuracy; and, together with simulation tools, recommends the optimum configuration for the neural topology and automatically generates synthesizable code for the hardware implementation tool. This is possible due to the design of parameter-dependent synthesis code and optimal hardware architecture design for both neural network and ELM training. Results show all the steps required to follow a successful design flow from the software tool to the final running device and, as an application example, the FPGA implementation for realtime detection of brain area in electrode positioning during a Deep Brain Stimulation (DBS) surgery is shown.