Arrays of silicon neurosensors have been fabricated in our group for detection of both electrical signals and neurotransmitter levels in human neuron cultures. Neurochemical sensing of dopamine and its metabolites is provided by voltammetry. Passive neurochemical arrays have been tested in living human neuron cultures throughout a study period of seventy-five days. Calibration curves for dopamine taken in culture media with equipment optimized for the sensors suggests detection limits for dopamine below 100nM. To improve response, prototype devices incorporating active circuitry were developed. These active devices were formed by post-processing standard CMOS die fabricated through the MOSIS service, to form the sensor-specific features. We also describe a fully-differential potentiostat which has been developed for implantable biological applications and briefly describe future directions for our work.

This paper covers recent developments in microfabricated potentiometric liquid chemical sensors. It includes a discussion of the various types of solid-state potentiometric sensors, including the inherent and practical challenges involved in implementing and commercializing the devices. The paper also presents recent advances that overcome some of these difficulties, including progress toward compatible microreference electrodes.

Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power savings by DVS alone is becoming limited as leakage power increases. In this paper, we show how the simultaneous use of adaptive body biasing (ABB) and DVS can be used to reduce power in high-performance processors. Analytical models of the leakage current, dynamic power, and frequency as functions of supply voltage and body bias are derived and verified with SPICE simulation. We then show how to determine the correct trade-off between supply voltage and body bias for a given clock frequency and duration of operation. The usefulness of our approach is evaluated on real workloads obtained using real-time monitoring of processor utilization for four applications. The results demonstrate that application of simultaneous DVS and ABB results in an average energy reduction of 48% over DVS alone.

On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase power consumption. As feature sizes shrink the dominant component of this power loss will be leakage. However, during a fixed period of time the activity in a cache is only centered on a small subset of the lines. This behavior can be exploited to cut the leakage power of large caches by putting the cold cache lines into a state preserving, low-power drowsy mode. Moving lines into and out of drowsy state incurs a slight performance loss. In this paper we investigate policies and circuit techniques for implementing drowsy caches. We show that with simple architectural techniques, about 80%-90% of the cache lines can be maintained in a drowsy state without affecting performance by more than 1%. According to our projections, in a 0.07 um CMOS process, drowsy caches will be able to reduce the total energy (static and dynamic) consumed in the caches by 50%-75%. We also argue that the use of drowsy caches can simplify the design and control of low-leakage caches, and avoid the need to completely turn off selected cache lines and lose their state.