This paper presents a novel technique for synthesis of speed-independentcircuits. It is based on partial order representation ofthe state graph called STG-unfolding segment. The new methoduses approximation technique to speed up the synthesis process.The method is illustrated on the basic implementation architecture.Experimental results demonstrating its efficiency are presented anddiscussed.

Article Free Access Share on Verification of asynchronous circuits using time Petri net unfolding Authors: Alexei Semenov Department of Computing Science, University of Newcastle, Newcastle upon Tyne NE1 7RU, England Department of Computing Science, University of Newcastle, Newcastle upon Tyne NE1 7RU, EnglandView Profile , Alexandre Yakovlev Department of Computing Science, University of Newcastle, Newcastle upon Tyne NE1 7RU, England Department of Computing Science, University of Newcastle, Newcastle upon Tyne NE1 7RU, EnglandView Profile Authors Info & Claims DAC '96: Proceedings of the 33rd annual Design Automation ConferenceJune 1996 Pages 59–62https://doi.org/10.1145/240518.240530Published:01 June 1996Publication History 24citation370DownloadsMetricsTotal Citations24Total Downloads370Last 12 Months8Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF