EPLX is the first high-level language used within the Bell System in writing Electronic Switching System (ESS) programs. An extension of a predecessor low-level language, it features structured control flow statements and data typing facilities. This paper stresses features of EPLX that allowed it to be incorporated into existing ESS software development tools and methods and into the software structure of an existing project (No. 4 ESS).

This paper presents a method of propagating the effects of faults through functional blocks using the deductive (fault list) technique. An extension of the method is shown to be effective for simulating internal faults in functional blocks. The techniques presented here have been used for implementing the functional simulation capability in the Logic Analysis for Maintenance Planning (LAMP) System at Bell Laboratories.

The effective use of simulation for logic verification and test evaluation frequently requires simulation capabilities at different levels of detail. This paper discusses the functional level simulation capability in the LAMP system at Bell Laboratories and its relation to gate level simulation. The Function Definition Language (FDL) used for specifying the behavior of functional blocks is discussed. Functions described in this language can be embedded in gate level circuits and simulated to determine the normal circuit behavior or faulty behavior. Classical faults external to functions and user specified internal faults in functions may be simulated. The effectiveness of functional simulation has been demonstrated in a number of applications such as memory modules in a large controller of an Electronic Switching System, the ROM in a small controller and an entire microprocessor treated as an interconnection of a few functional blocks.

A comparison of the central processing unit (CPU) time and storage requirements for the parallel and deductive fault simulation techniques is presented. Versions of a parallel and deductive simulator were implemented and the comparison performed on an IBM System/360 Model 67 by simulating representative circuits including shift registers, sequencers, counters, two memory units, and a processor. The results indicate that the deductive technique requires less CPU time for "loosely sequential" circuits or circuits having large numbers of simulated faults (e.g., >1000). The parallel technique is faster for small (e.g., <500 gates) "highly sequential" circuits or for small numbers of simulated faults. The storage required for a parallel simulator, however, can always be less than that required for a deductive simulator. In general, if sufficient memory is available, the deductive simulator is the more cost-effective simulator when a wide range of circuits is to be simulated and only one type of simulator is available. A substantial savings in logic circuit development cost can be realized when the proper simulation technique is used for logic design verification, fault analysis, and the generation of diagnostic data.