The most widely used open-source field-programmable gate array (FPGA) placement and routing tool is VPR, which can define the target FPGA, perform placement and routing, and report area and timing information. However, it cannot be used in FPGA IP design efficiently for two reasons. First, for most newly developed FPGA architectures, VPR cannot support them directly. Modifying the C-coded VPR for using it to evaluate a number of new architectures requires a long time. Second, the accuracy of the VPR performance results is not enough for the evaluation of a complete synthesizable FPGA IP in the design that targets the productions of LSI. We propose a FPGA design framework that in particular improves FPGA IP design efficiency. A novel FPGA routing tool is developed in this framework, namely EasyRouter. EasyRouter is developed using the C# language. When an object-oriented programming method is used, the source codes are fewer and easier manage compared to VPR, which shortens the development time. By using simple HDL templates, EasyRouter can automatically generate entire chip HDL codes and the configuration bitstream. With these files, the FPGA IP can be evaluated with commercial VLSI CADs with high accuracy and reliability.

In this paper, we propose fault-tolerant field-programmable gate array (FPGA) architectures and their computer-aid design (CAD) for intellectual property (IP) cores in system large-scale integration (LSI). Unlike discrete FPGAs, in which the integration scale can be made relatively large, programmable IP cores must correspond to arrays of various sizes. The key features of our architectures are regular tile structure, spare modules and bypass wires for fault avoidance, and configuration mechanism for single-cycle reconfiguration. In addition, we develop routing tools, namely EasyRouter for proposed architecture. This tool can handle various array sizes corresponding to developed programmable IP cores. In this evaluation, we compared the performances of conventional FPGA and the proposed fault-tolerant FPGA architectures. On average, our architectures have less than 2.2 times the area and 1.3 times the delay compared with conventional FPGA architectures. At the same time, conventional FP-GAs cannot tolerate faults, whereas our architectures perform with a 90% success rate in fault avoidance for a ratio of faulty tiles of 1% or less.

Although redundancy techniques are generally used to provide fault tolerance for the system large scale integrations (LSIs), these techniques have significantly costs. However, field programmable gate arrays (FPGAs) can easily provide high reliability due to their reconfiguration ability. The present paper proposes an effective fault detection method for the global interconnects of the FPGA. In the proposed method, by combining different kinds of test patterns, the fault resources can be identified. We also developed placement and routing tools to avoid fault resources in two cases, namely, tile-level avoidance and multiplexer-level avoidance. In the evaluation of the proposed technique, the proposed detection method diagnosed a defect multiplexer with six test configurations. We found that the fault FPGA can achieve the same performance as normal FPGA in multiplexer-level avoidance.

Generally, a programmable LSI such as an FPGA is difficult to test as compared to an ASIC. There are two major reasons for this. One is that automatic test pattern generator (ATPG) cannot be used because of the programmability of the FPGA. The other reason is that the FPGA architecture is very complex. In this paper, we propose a novel FPGA architecture that will simplify the testing of the device. The architecture is very simple and has several types of circuit blocks and orderly wire connections. This paper also presents efficient test configurations for our proposed architecture. We tested the interconnects of our architecture by using our configurations and achieved 100% test coverage for a short test time.

Generally, a programmable LSI such as an FPGA is difficult to test compared to an ASIC. There are two major reasons for this. One is that automatic test pattern generator (ATPG) cannot be used because of the programmability of the FPGA. The other reason is that the FPGA architecture is very complex. In this paper, we propose a new FPGA architecture that will simplify the testing of the device. The base of our architecture is general island-style FPGA architecture, but it consists of a few types of circuit blocks and orderly wire connections. This paper also presents efficient test configurations for our proposed architecture. We tested the interconnects of our architecture by using our configurations and achieved 100% test coverage for a short test time.

In the present study, we investigate the use of reconfigurable logic devices (RLDs) as intellectual properties (IPs) for system on a chip (SoC). Using RLDs, SoCs can achieve both high performance and high flexibility. However, conventional RLDs have problems related to performance, area, and power consumption. In order to resolve these problems, we investigated the features of RLD architecture. RLDs are classified into fine-grained and coarse-grained devices based on their architecture. Generally, the granularity of an RLD is limited to either type, which means that a device can only achieve high performance in applications that are suited to its architecture. Therefore, we propose a variable-grain logic cell (VGLC) architecture that can overcome the trade-off between fine-grained and coarse-grained architectures, which are required for the implementation of random and arithmetic logics, respectively. The VGLC is based on a 4-bit adder including configuration bits, which can perform arithmetic and random logic operations unlike the LUT. In the present paper, a local interconnection architecture for the VGLC is proposed. Several types of local interconnections composed of different crossbars are compared, and the trade-off between hardware resources and flexibility is discussed. Using local interconnection, the routing area is reduced by a maximum of 49%.