Demo Data from EDBT 2026 / reviewers in the wild / expert
Igal Kohavi
dblp:43/4333
· DBLP profile ↗
5ranked-venue papers
2as first author
0since 2021 · last 1974
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-authorDatabases, data management, data science and information retrieval · 1Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 91% Integrated circuit design · 9% | |
| Theoretical computer science
1 paper |
Computational complexity · 100% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.0 | 2 | 1972 | Detection of Multiple Faults in Combinational Logic Networks · IEEE Trans. Computers 1972 Variable-Length Distinguishing Sequences and Their Application to the Design of Fault-Detection Experiments · IEEE Trans. Computers 1968 |
Electronic design automation › hardware verification and test › fault detection
multiple fault detection |
0.0 | 1 | 1972 | Detection of Multiple Faults in Combinational Logic Networks · IEEE Trans. Computers 1972 |
Electronic design automation › hardware verification and test
test generation |
0.0 | 1 | 1972 | Detection of Multiple Faults in Combinational Logic Networks · IEEE Trans. Computers 1972 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1967 | On Minimal Modulo 2 Sums of Products for Switching Functions · IEEE Trans. Electron. Comput. 1967 |
Electronic design automation › hardware verification and test
fault-detection experiment |
0.0 | 1 | 1968 | Variable-Length Distinguishing Sequences and Their Application to the Design of Fault-Detection Experiments · IEEE Trans. Computers 1968 |
Electronic design automation › logic synthesis › switching theory
switching function |
0.0 | 1 | 1967 | On Minimal Modulo 2 Sums of Products for Switching Functions · IEEE Trans. Electron. Comput. 1967 |
Electronic design automation › logic synthesis
sequential circuit synthesis |
0.0 | 1 | 1968 | Variable-Length Distinguishing Sequences and Their Application to the Design of Fault-Detection Experiments · IEEE Trans. Computers 1968 |
Computational complexity › boolean function analysis
symmetric functions |
0.0 | 1 | 1967 | On Minimal Modulo 2 Sums of Products for Switching Functions · IEEE Trans. Electron. Comput. 1967 |
Methods — techniques the papers use, named apart from their topics
test-equivalence relation · 0.0test-covering relation · 0.0term-count lower bound · 0.0modulo 2 sum of products realization · 0.0diagnosing tree · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1974 | Checking experiments for sequential machines
Zvi Kohavi, J. A. Rivierre, Igal Kohavi |
Inf. Sci. | 3 |
| 1973 | Machine Distinguishing ExperimentsabstractThis paper describes procedures for the design of experiments that distinguish a given n-state machine from all other machines which have n states or less. Such experiments can also be used in certain cases to determine whether or not a given machine is operating correctly. We shall be mainly concerned with finite-state, strongly connected machines which are in a reduced form. Zvi Kohavi, J. A. Rivierre, Igal Kohavi |
Comput. J. | 3 |
| 1972 | Detection of Multiple Faults in Combinational Logic NetworksabstractNew techniques are presented for generating fault-detection experiments for combinational logic networks. Only single-output functions are considered. Test-covering and test-equivalence relations between networks are defined and these relations are shown to be Instrumental in generating the experiments. The techniques presented provide minimal experiments for detecting multiple faults In two-level networks and provide nearly minimal experiments for most other networks. Igal Kohavi, Zvi Kohavi |
IEEE Trans. Computers | 1 |
| 1968 | Variable-Length Distinguishing Sequences and Their Application to the Design of Fault-Detection ExperimentsabstractAbstract—A variable-length distinguishing sequence (VLDS) is a preset distinguishing sequence X0such that, if the machine is started in an unknown state, the output response of the machine to some prefix of X0will identify the initial state. The length of the required prefix is a function of the initial state. The properties of such sequences are investigated and a method which employs a modified version of the diagnosing tree is developed for generating and displaying all such sequences. The fixed-length distinguishing sequence (FLDS) is shown to be a special case of the more general VLDS. The VLDS is next applied in the design of simple and efficient preset fault-detection experiments for sequential machines. Igal Kohavi, Zvi Kohavi |
IEEE Trans. Computers | 1 |
| 1967 | On Minimal Modulo 2 Sums of Products for Switching FunctionsabstractThe minimal number of terms required for representing any switching function as a modulo 2 sums of products is investigated, and an algorithm for obtaining economical realization is described. The main result is the following: every symmetric function of 2m+1 variables has a modulo 2 sum of products realization with at most 3mterms; but there are functions of n variables which require at least 2n/n log23 terms for sufficiently large n. Shimon Even, Igal Kohavi, Azaria Paz |
IEEE Trans. Electron. Comput. | 2 |