6G non-terrestrial networks (NTNs) will use satellites for global internet access, where low earth orbit (LEO) satellites will be used frequently due to the lower latency and higher link budget that can be provided compared to higher altitude satellites. However, LEO satellites require many satellites due to their fast movement and limited coverage, leading to frequent handovers (HOs). This paper presents an intelligent LEO satellite conditional handover (ILCHO) scheme that improves the NTN performance by addressing the frequent HO issues while reducing the signal strength variation between cells and outdated measurement values. The ILCHO scheme derives the LEO satellite's state information (position and orbital path), which is used to obtain the conditions for a LEO satellite to be accessible to enable optimized target LEO satellite selection that will maximize the overall network service performance while minimizing the number of HOs. The ILCHO scheme uses multi-agent reinforcement learning (MARL) to maintain an optimized performance through early preparation by incorporating a distance-based event in the execution phase. The simulation results show that the proposed ILCHO scheme can increase the throughput and signal to noise ratio (SNR) performance compared to other HO algorithms, thereby providng improved and more stable communication conditions.

In this paper, a trajectory optimization algorithm for multiple unmanned aerial vehicles (UAVs) is investigated for free space optic (FSO) based wireless communication networks, which is composed of multiple UAVs and multiple ground terminals (GTs). Considering the FSO channel model and line of sight (LoS) probability, the altitude of the UAVs for FSO connection between each GT and UAV is decided by the predetermined radius of the communication area of the GT. A multi-UAV trajectory optimization (MUTO) scheme is proposed to maximize the service time. In the MUTO scheme, first, the network is divided into multiple sectors using graph partitioning, and assigned to each UAV, and then the traveling salesman problem (TSP) is used to determine the order of the GTs that the UAV passes through. The number of UAVs that maximizes the time for the UAV to stay within the communication area of the GT is derived. The UAV trajectories are determined by sequentially minimizing the energy consumed when moving between GTs and maximizing the service time by applying successive convex approximation. In addition, to assist operations that use multiple UAVs, two collision avoidance schemes are applied to the MUTO scheme. First is the additional constraints (AC) method, which uses a geographic formula to control the distance between the UAVs, and second is the initial delay (ID) method, which deliberately adds a delay to the UAV trajectories to provide sufficient UAV spacing. The simulation results show that under low density operation conditions, MUTO-ID and MUTO-AC are sufficient to avoid all UAV collisions, and in overly dense UAV operations with very close UAV trajectories, MUTO-ID can reduce collisions by approximately 80%, MUTO-AC can reduce collisions by approximately 85%, and MUTO-ACID can reduce collisions by approximately 95%, when compared to the MUTO scheme with no collision avoidance support applied.

To increase the sense of immersion of 360VR images, we have proposed and implemented foveated rendering technology through precision region-of-interest detection using eye-tracking-based head-mounted display equipment for a high-efficiency video coding tiled video-based image-decoding and -rendering method. Our method can provide a high rendering speed and high-quality textures.

This paper shows how a system was designed and implemented for the live tiled streaming of 360° Virtual Reality(VR) eSports based on HEVC. A virtual camera technique was designed and implemented based on the Unity and Unreal engines as a means of capturing 360° videos in a virtual space, and a MPEG-DASH SRD(Spatial Relation Description)[1-2] Based dashing and streaming server was configured to build a live HEVC encoding system and for real-time internet streaming. Finally, an integrated 360° VR client was configured for use as a multi-platform. Each technological element was designed to service the client through a 360° VR 3D stereo method, and the MPEG-DASH SRD was expanded such that high-quality game videos can be played at lower bandwidths.

In three-dimensional video (3DV), two cameras capture the same scene from different viewpoints. Color and focus variations between the camera views may deteriorate the 3DV quality and performance of 3DV coding. Therefore, we need to correct the color and focus discrepancy between the camera views. In this paper, we propose algorithms that color and focus correction are combined in a preprocessing step of the stereo video coding. For both color and focus matching, we calculate only disparity vector (DV) once during disparity estimation (DE), since the proposed color and focus correction algorithm can share the disparity vector. The experimental results show that the proposed color and focus correction algorithm provides better image quality and coding performance.

Multiview video coding (MVC) provides more realistic 3-D scenes adding depth information derived from multiple cameras than single-or stereo-view video coding. In MVC, video frames obtained from each view are simply scheduled to corresponding encoding channels. However, under such a conventional scheduling technique the encoding times of each channel may not be identical, degrading encoding performance. To address this problem, this paper proposes two MVC frame scheduling schemes and their architectures: a hardware resource aware scheduling and a frame waiting time aware scheduling (WTaS). Here, WTaS considers the waiting time of each frame stored in on-chip SRAM during frame scheduling, thereby reducing SRAM size significantly. Experimental results show that the proposed frame scheduling schemes provide 29.4% faster processing time, compared to the conventional counterpart. In addition, we can improve the core area, on-chip SRAM area, and the power dissipation by 26.7%, 23.2%, and 26.6%, respectively.

With the massive deployment of mobile devices and sensor networks, resistance against side-channel attacks in cryptographic systems has become an active research topic in recent years. While various security measures exist in literature, most of them are deterministic in nature, where the same input plaintext always results in the same power trace with a given key. Thus, attackers can still aggregate the small deviations between the power traces to identify the correct key. Towards this, random dynamic voltage scaling has been proposed in the literature, which is demonstrated to be effective against Differential Power Analysis (DPA). In this paper, we evaluate this approach, along with the expanded feature of spatial randomness, to resist Correlation Power Analysis (CPA).

Image rectification is one of the most complex pre-processing techniques for multi-view video coding (MVC). It corrects image distortion and simplifies MVC matching operations by transforming images into a standard coordinate system. Therefore, the rectification can improve both image quality and coding efficiency for MVC. In this paper, we propose two low complexity image rectification schemes for MVC: view-selective preprocessing rectification and view-selective pre- and post-processing rectification. The proposed algorithm does not perform frames of all views but few selected views which do not affect MVC performances. The experimental results show that the proposed rectification schemes feature much lower complexity without degrading image quality than the existing approach.

While multi-view video system offers users various three-dimensional scenes, its hardware architecture requires more power consumption, chip size and processing time. Each view in Group of Group of Pictures (GoGoP) has different frame structure and different number of reference frames. The multi-view video coding (MVC) performance heavily relies on the frame scheduling architecture for motion estimation (ME) and disparity estimation (DE). Therefore, we need to develop efficient frame scheduling schemes for MVC. In this paper, we propose two frame scheduling schemes: hardware resource aware scheduling (HRaS) and buffering time aware scheduling (BTaS). In the proposed scheduling schemes, the GoGoP is represented by a graph in which edges represent relationship between reference frames and current frames. HRaS relocates frames in GoGoP so that total hardware resources for MVC prediction are reduced. BTaS relocates the frames based on the number of edges so that prediction time and buffering time of the frames are reduced. Through experimental results, we verified the efficiency of the proposed scheduling architectures in terms of power dissipation, area, MVC prediction time, and buffering time.

Modulo 2n+ 1 multiplier is one of the critical components in the area of data security applications such as International Data Encryption Algorithm (IDEA), digital signal processing, and fault-tolerant systems that demand high reliability and fault tolerance. Transient faults caused by electrical noise or external interference are resulting in soft errors which should be detected online. The effectiveness of the residue codes in the self-checking implementation of the modulo multipliers has been rarely explored. In this paper, an efficient hardware implementation of the self-checking modulo 2n+ 1 multiplier is proposed based on the residue codes. Different check bases in the form 2c-1 or 2c+ 1 (c ϵσ N) are selected for various values of the input operands. In the implementation of the modulo generators and modulo multipliers, novel multiplexor-based compressors are applied for efficient modulo 2n+ 1 multipliers with less area and lower power consumption. In the final addition stage of the modulo multipliers and modulo generators, efficient sparse-tree-based inverted end around carry adders are used. The proposed architecture is capable of online detecting errors caused by faults on a single gate at a time. The experimental results show that the proposed self-checking modulo 2n+ 1 multipliers have less area overhead and low performance penalty.

Carbon Nanotube FET technology is a new promising technology for high speed digital applications. This paper investigates optimizing analog circuits architecture to take advantage of this technology in mixed mode ICs. It was found through simulations that the optimum topology for high-bandwidth analog circuits is obtained by using an architecture which avoids loading by the high CNFET gate capacitance in the main signal path at high impedance points. Low junction capacitances of CNFET and high transconductance (gm) compared to silicon MOSFET indicates that high gain-bandwidth can be obtained by using CNFET. Simulations indicate low voltage operation (0.5 V) is possible using CNFET technology and also high temperature operation (> 200 C) is possible. Monte-Carlo simulations indicate that device matching of important CNFET parameters such as nanotube diameter, channel length, source/drain doping are important to get consistent results.

In this work, a novel asynchronous combinational S-Box (substitution box) design for AES (Advanced Encryption Standard) cryptosystems is proposed and validated. The S-Box is considered as the most critical component in AES crypto-circuits since it consumes the most power and leaks the most information against side-channel attacks. The proposed design is based on a delay-insensitive logic paradigm known as Null Convention Logic (NCL). The proposed NCL S-Box provides considerable benefits over existing designs since it consumes less power therefore suitable for energy-constrained mobile crypto-applications. It also emits less noise and has flatter power peaks therefore leaks less information against side-channel attacks such as differential power/noise analysis. Functional verification, analog simulation and power measurement of NCL S-Box have been done using Mentor Graphics EDA (Electronic Design Automation) tools to assure low-power side-channel attack-resistant operation of the proposed clock-free AES S-Box design.

The six papers in this special section cover a wide spectrum of techniques which are encountered in the design of circuits and systems for nano-scale computing.

We present an approach for fault detection in layered interconnection networks (LINs). An LIN is a generalized multistage interconnection network commonly used in reconfigurable systems; the nets (links) are arranged in sets (referred to as layers) of different size. Switching elements (made of simple switches such as transmission-gate-like devices) are arranged in a cascade to connect pairs of layers. The switching elements of an LIN have the same number of switches, but the switching patterns may not be uniform. A comprehensive fault model for the nets and switches is assumed at physical and behavioral levels. Testing requires configuring the LIN multiple times. Using a graph approach, it is proven that the minimal set of configurations corresponds to the node disjoint path sets. The proposed approach is based on two novel results in the execution of the network flow algorithm to find node disjoint path sets, while retaining optimality in the number of configurations. These objectives are accomplished by finding a feasible flow such that the maximal degree can be iteratively decreased, while guaranteeing the existence of an appropriate circulation. Net adjacencies are also tested for possible bridge faults (shorts). To account for 100 percent fault coverage of bridge faults a postprocessing algorithm may be required; bounds on its complexity are provided. The execution complexity of the proposed approach (inclusive of test vector generation and post-processing) is O(N/sup 4/WL), where N is the total number of nets, W is the number of switches per switching element, and L is the number of layers. Extensive simulation results are provided.

A highly dependable embedded fault-tolerant memory architecture for high performance massively parallel computing applications and its dependability assurance techniques are proposed and discussed in this paper. The proposed fault tolerant memory provides two distinctive repair mechanisms: the permanent laser redundancy reconfiguration during the wafer probe stage in the factory to enhance its manufacturing yield and the dynamic BIST/BISD/BISR (built-in-self-test-diagnosis-repair)-based reconfiguration of the redundant resources in field to maintain high field reliability. The system reliability which is mainly determined by hardware configuration demanded by software and field reconfiguration/repair utilizing unused processor and memory modules is referred to as HW/SW Co-reliability. Various system configuration options in terms of parallel processing unit size and processor/memory intensity are also introduced and their HW/SW Co-reliability characteristics are discussed. A modeling and assurance technique for HW/SW Co-reliability with emphasis on the dependability assurance techniques based on combinatorial modeling suitable for the proposed memory design is developed and validated by extensive parametric simulations. Thereby, design and Implementation of memory-reliability-optimized and highly reliable fault-tolerant field reconfigurable massively parallel computing systems can be achieved.

This paper investigates the co-effect of hardware and software on the reliability as measured by quality level (or defect level) of configurable multichip module (CMCM) systems. Hardware architecture of CMCM can be configured to accommodate target application design. An application, as provided in a form of software, is partitioned and mapped on the provided configurable hardware. Granularity of an application can be used as a criteria of partitioning and mapping, and can determine the utilization pattern of hardware resources. The utilization pattern of CMCM determines the configuration strategy of available hardware resources based on the application's granularity. Different utilization patterns of an application design on CMCM may result in various impacts on escape tolerance (i.e. the probability to avoid inclusion of hardware resources in the configuration that escaped from testing). A quality level model of CMCM is proposed to capture and trace the co-effect of hardware and software, referred to as co-reliability, with respect to escape-tolerance. Various configuration strategies are proposed and evaluated against various criterion granularity and utilization distributions based on the proposed models and evaluation techniques. Extensive analytical and parametric simulation results are shown.

This paper presents a new model for analyzing the yield of MCM systems with repair process. It exploits the connectivity of the interconnected chips in which yield degradation due to both neighboring chips and interconnect structure are taken into account. Based on the connectivity, two MCM repair scheduling strategies, Smallest Number of Interconnections First (SNIF) and Smallest Number of Neighboring Chips First (SNCF) are proposed Two other scheduling strategies, Largest Number of Interconnections First (LNIF) and Largest Number of Neighboring Chips First (LNCF) are also introduced and analyzed to further explore the impact of connectivity-based repair scheduling on the overall yield of MCMs. Extensive parametric simulations demonstrate the efficiency of the proposed MCM repair scheduling strategies.