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C.-T. Hsieh

dblp:43/4826 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
power analysis
0.112006
Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Electronic design automation
hardware verification and test
0.012006
Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006

Methods — techniques the papers use, named apart from their topics

vectorless analysis · 0.1signal correlation analysis · 0.1graph algorithms · 0.1
YearPublicationVenuePosition
2006 Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits
abstract
Large current in a chip can cause problems such as noise and power consumption. In this paper, a vectorless approach to analyzing a tight upper bound on the maximum instantaneous current (MIC) of a circuit is proposed. Several types of signal correlations that can cause the MIC estimation to lose accuracy are first described. Next, taking signal correlations into account, theorems to identify gates that switch mutually exclusively are proposed. In particular, the proposed algorithm can naturally consider signal correlations across sequential elements (flip-flops), whereas previous research on this topic addressed combinational circuits only. After deriving the information of mutually exclusive switching, a graph algorithm is applied to obtain an upper bound on the MIC. On average, the obtained sequential benchmark results are 179% tighter than those from the iMax algorithm and 66% tighter than those from the partial input enumeration algorithm
C.-T. Hsieh, J.-C. Lin, Shih-Chieh Chang 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1