Demo Data from EDBT 2026 / reviewers in the wild / expert
Chitoor V. Srinivasan
dblp:43/4876
· DBLP profile ↗
5ranked-venue papers
5as first author
0since 2021 · last 1976
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 4 first-authorArtificial intelligence and machine learning · 1 · 1 first-authorGraphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Hardware reliability and fault tolerance · 83% Electronic design automation · 17% | |
| Artificial intelligence
2 papers |
Knowledge representation and reasoning · 77% Planning, search and constraint satisfaction · 23% |
Topics — the 7 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Knowledge, reasoning and agents › Knowledge representation and reasoning › cognitive modeling › cognitive architecture
problem-solving architecture |
0.0 | 1 | 1976 | The Architecture of Coherent Information System: A General Problem Solving System · IEEE Trans. Computers 1976 |
Hardware reliability and fault tolerance
error-correcting codes for memory |
0.0 | 2 | 1971 | Codes for Error Correction in High-Speed Memory Systems Part II: Correction of Temporary and Catastrophic Errors · IEEE Trans. Computers 1971 Codes for Error Correction in High-Speed Memory Systems - Part I: Correction of Cell Defects in Integrated Memories · IEEE Trans. Computers 1971 |
Hardware reliability and fault tolerance
error correction |
0.0 | 2 | 1971 | Codes for Error Correction in High-Speed Memory Systems Part II: Correction of Temporary and Catastrophic Errors · IEEE Trans. Computers 1971 Codes for Error Correction in High-Speed Memory Systems - Part I: Correction of Cell Defects in Integrated Memories · IEEE Trans. Computers 1971 |
Hardware reliability and fault tolerance
memory reliability |
0.0 | 2 | 1971 | Codes for Error Correction in High-Speed Memory Systems Part II: Correction of Temporary and Catastrophic Errors · IEEE Trans. Computers 1971 Codes for Error Correction in High-Speed Memory Systems - Part I: Correction of Cell Defects in Integrated Memories · IEEE Trans. Computers 1971 |
Electronic design automation
hardware description language |
0.0 | 1 | 1969 | A discussion of CDLI, a computer description language and associated design aid systems · DAC 1969 |
Electronic design automation › hardware synthesis
automatic synthesis |
0.0 | 1 | 1969 | A discussion of CDLI, a computer description language and associated design aid systems · DAC 1969 |
Electronic design automation
logic synthesis |
0.0 | 1 | 1969 | A discussion of CDLI, a computer description language and associated design aid systems · DAC 1969 |
Methods — techniques the papers use, named apart from their topics
metasystem architecture · 0.0knowledge-based reasoning · 0.0error-correcting codes · 0.0parallel decoding nets · 0.0parallel decoding · 0.0formal description language · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1976 | The Architecture of Coherent Information System: A General Problem Solving SystemabstractThis paper discusses the architecture of a metasystem, which can be used to generate intelligent information systems for different domains of discourse. It points out the kinds of knowledge accepted by the system, and the way the knowledge is used to do nontrivial problem solving. The organization of the system makes it possible for it to function in the context of a large and expanding data base. The metasystem provides a basis for the definition of the concept of machine understanding in terms of the models that the machine can build in a domain, and the way it can use the models. Chitoor V. Srinivasan |
IEEE Trans. Computers | 1 |
| 1973 | The Architecture of Coherent Information System: A General Problem Solving System
Chitoor V. Srinivasan |
IJCAI | 1 |
| 1971 | Codes for Error Correction in High-Speed Memory Systems - Part I: Correction of Cell Defects in Integrated MemoriesabstractThis paper introduces two schemes to correct bit errors caused by defective memory cells in high-speed random-access memory systems. The schemes are addressed to word-organized memories produced by the integrated technologies. One of the two schemes calls for encoding of input information and the other does not. The schemes are simple, economical for the technologies concerned, and exhibit a regularity which makes it possible to fabricate the necessary additional hardware within the same technology. Chitoor V. Srinivasan |
IEEE Trans. Computers | 1 |
| 1971 | Codes for Error Correction in High-Speed Memory Systems Part II: Correction of Temporary and Catastrophic ErrorsabstractA few classes of codes, suitable for error correction in high-speed memory systems, are presented. The codes have relatively simple parallel decoding nets. The codes may be used for the correction of both temporary and catastrophic errors. Chitoor V. Srinivasan |
IEEE Trans. Computers | 1 |
| 1969 | A discussion of CDLI, a computer description language and associated design aid systemsabstractCDLI is a formal language for describing hardware and software computing systems in various stages of design. As a formal language to talk about systems of this kind, CDLI provides a linguistic basis to consider machine aided solutions to a variety of design problems. In the context of CDLI, we are envisioning at present systems for design documentation, data retrieval, editing, design analysis, simulation and eventually automatic synthesis. The creation of a powerful and flexible descriptive data base is the key conceptual and technical problem that we must solve to implement these systems. The features introduced in the description language, CDLI, and the kinds of processors that are being developed for the documentation system are intended as solutions for this problem. The system so created will give us a point of departure for further explorations in this area through experimentation. Chitoor V. Srinivasan |
DAC | 1 |