A cell-based test design method which is consistent with features of cell-based design is introduced. By improving shift register latches, a scan test for asynchronous circuits, as well as delay tests can be executed effectively. Also, by employing a test bus and a selector shift register configuration, a multiple scan-path test is realized attractively, which drastically reduces the execution time of the scan test. This results in the possibility of realizing a hierarchical test design in which the test vectors of module circuits are saved as library data and used in the preparation of the test vector of a newly developed chip and of the schematic and artwork data. It appears that the area overhead and the increase in test time are reasonable for future VLSI chips with the complexity of 1M transistors.>

The propagation delay time of the ED MOS logic gate is precisely analyzed considering input waveform and loading conditions. According to theoretical consideration and circuit analysis, the rise mode delay time tpLH is approximated as a function of the output capacitance of only the gate concerned. The fall mode delay time t.pHL is determined by the input capacitance and output capacitance of the gate concerned. These results allow the easy implementation of the delay model into a logic simulator. A precise delay simulation is attained by considering the delay components, corresponding to each input node, at the output side of the logic element. The propagation delay times of the transmission gate are precisely analyzed. The operations of the transmission gate are divided into two modes; synchronous mode and asynchronous mode. Corresponding to each mode, the transmission gate, the preceding gate, and the succeeding gate have two kinds of delay times. To simulate delay times of each gate precisely, models which treat these three logic elements as one primitive element in a logic simulator have been proposed. The new timing verification method using the delay model is evaluated with respect to delay-time accuracy and execusion time in a logic LSI. Through this method, circuit simulator accuracy is obtained in the short computer run time of a logic simulator.