This paper presents a generalized earliest-first (GEF) addition algorithm to accelerate carry propagation addition (CPA). A set of operators and notations have been developed to describe and analyze traditional carry-lookahead or conditional-sum-based algorithms. The proposed GEF algorithm schedules bit-level operations of CPA in an earliest-first manner to reduce the overall latency. With the aid of the developed operators and notations, the algorithm can be generalized to any algorithm based on carry-lookahead or conditional-sum rule. An adder generated by using the GEF algorithm outperforms traditional algorithms when inputs do not arrive simultaneously.

Real-time three-dimensional (3D) graphics is emerging rapidly in multimedia applications, but it suffers from requirements for huge computation, high bandwidth, and large buffer. In order to achieve hardware efficiency for 3D graphics rendering, we propose a novel approach named index rendering. The basic concept of index rendering is to realize a 3D rendering pipeline by using asynchronous multi-dataflows. Triangle information can be divided into several parts with each part capable of being transferred independently and asynchronously. Finally, all data are converged by the index to generate the final image. The index rendering approach can eliminate unnecessary operations in the traditional 3D graphics pipeline, the unnecessary operations are caused by the invisible pixels and triangles in the 3D scene. Previous work, deferred shading, eliminates the operations relating to invisible pixels, but it requires huge tradeoffs in bandwidth and buffer size. With index rendering, we can eliminate operations on both invisible pixels and triangles with fewer tradeoffs as compared with the deferred shading approach. The simulation and analysis results show that the index rendering approach can reduce 10%-70% of lighting operations when using the flat and Gouraud shading process and decrease 30%-95% when using Phong shading. Furthermore, it saves 70% of buffer size and 50%-70% of bandwidth compared with the deferred shading approach. The result also indicates that this approach of index rendering is especially suitable for low-cost portable rendering devices. Hence, index rendering is a hardware-efficient architecture for 3D graphics, and it makes rendering hardware more easily integrated into multimedia systems, especially system-on-a-chip (SOC) designs.

In this paper, we present a carry-save to signed-digit (CS2SD) recoder with high performance and small area. The recoder can be employed in common fused addition-multiplication operation which is widely used in various signal-processing applications. Our design shows 18% area-time product improvement over the traditional designs.

Real-time 3-D graphics emerges rapidly in multimedia applications, but suffers from huge computation requirement. In 3-D graphics, lighting is an essential operation, but requires high computation power. In fact, many lighting calculations are redundant due to invisible polygons. To explore computation efficiency, we propose a novel deferred lighting approach. This approach defers lighting calculation after visibility comparison, hence eliminates lighting calculation on invisible polygon. Simulation result shows that deferred lighting approach can save 22%-58% of lighting calculation in flat shading and Gouraud shading, and initial cost of Taylor series in fast Phong shading.

This paper presents a design methodology for high-speed Booth encoded parallel multiplier. For partial product generation, we propose a new modified Booth encoding (MBE) scheme to improve the performance of traditional MBE schemes. For final addition, a new algorithm is developed to construct multiple-level conditional-sum adder (MLCSMA). The proposed algorithm can optimize final adder according to the given cell properties and input delay profile. Compared with a binary tree-based conditional-sum adder, the speed performance improvement is up to 25 percent. On average, the design developed herein reduces the total delay by 8 percent for parallel multiplier. The whole design has been verified by gate level simulation.