In this paper, we introduce PFPSim, a host-compiled simulator for early validation and analysis of packet processing applications on programmable forwarding plane architectures. The simulation model is automatically generated from a high-level description of the hardware/software architecture of the forwarding device and the behavioral description of the various modules in the architecture. Our high-level architectural description language is capable of defining many-core network processors as well as reconfigurable pipelines. The behavior of the fixed-function processing elements in the architecture is defined in C++. The code targeted for the processor cores, or reconfigurable pipeline stages, is compiled from P4, an emerging programming language for packet processing applications. Application developers can use PFPSim as a virtual prototype to simulate and debug their applications before hardware availability. Moreover, forwarding device architects can use PFPSim to evaluate the trade-offs between different hardware/software design decisions.

This paper presents a novel dynamically reconfigurable active L1 cache model for hybrid prototyping, called DRAC. The hybrid prototyping technique simulates a multicore embedded system using an emulation kernel on top of a single physical instance of a core. We extend hybrid prototyping by supporting memory hierarchy modeling with DRAC. The presented cache model is a standalone cycle accurate model that is further customized for multicore emulation. DRAC run-time configurability enables the embedded system designer to simulate and explore different multicore design options without the need for full FPGA prototyping. Our experimental results show 2.78% average error and 5.06% worst case error when DRAC is used as a standalone cache model in a single core design. We also observed 100% relative accuracy and less than 13% absolute worst case error in timing estimation when DRAC is used for hybrid prototyping of multicore designs.

This paper presents a novel modeling technique for multicore embedded systems, called Hybrid Prototyping. The fundamental idea is to simulate a design with multiple cores by creating an emulation kernel in software on top of a single physical instance of the core. The emulation kernel switches between tasks mapped to different cores and manages the logical simulation times of the individual cores. As a result, we can achieve fast and cycle-accurate simulation of symmetric multicore designs, thereby overcoming the accuracy concerns of virtual prototyping and the scalability issues of physical prototyping. Our experiments with industrial multicore designs show that the simulation time with hybrid prototyping grows only linearly with the number of cores and the inter-core communication traffic, while providing 100% cycle accuracy.

This paper presents a configurable and observable model of L1 data cache memory and a novel method for integrating the model into an FPGA prototype. Embedded system software designers use in-circuit emulation on FPGA platforms to validate the functionality and performance of embedded software. Data cache, particularly L1, has a major impact of system performance, yet remains unobservable during software debugging and analysis. Our solution is to model the data cache as an on-chip hardware peripheral that can be integrated into the processor system and can display the state of the data cache at any given time. The model is synthesized on Xilinx Virtex 5 FPGA and validated using several benchmarks. The experimental results show that the model can accurately track cache hits and misses and can estimate the run time of an embedded software application with an average error of only 5.4%, and a worst case error of only 13.7%.

This paper presents methods for automatic generation of models of Transducer, a highly flexible communication module for interfacing Multiprocessor System-on-Chip (MPSoC) components. We describe the transducer architecture, comprising the bus interface, high-level communication controllers and buffer management blocks. The well-defined architecture of the transducer enables automatic generation of its Transaction-level and Register-transfer level (RTL) models. Moreover, the simple interface of the transducer provides for a well-defined software interface, making it easy to update the software after changes in MPSoC platform. Our experimental results show that MPSoC design for industrial-size applications, such as MP3 decoder and JPEG encoder, greatly benefits from automatic generation of transducer models. We found productivity gains of 9-23× due to significant savings in modeling effort. On the quality axis, we show that MPSoC communication design using automatically generated transducers has very little overhead in communication delay over a fully connected point-to-point communication architecture. Finally, we show that our automatically generated TLMs greatly reduce the system-level modeling time and provide a fast executable model for early functional validation.

This paper describes a methodology for developing abstract and executable system-level model in SystemC of real-time embedded software, targeted to an RTOS. Our objective is to reuse as much of the software as possible to minimize model development time. Therefore, we design a RTOS emulation layer on top of the SystemC kernel. The application software is linked against the emulation layer to create an executable model of the software. The model can be integrated into system level HW-SW models which can be used for fast, accurate and early system validation. We validated our models using industrial-size examples such as MP3 decoder and Vocoder. The experimental results show that our models are very accurate and significantly faster than software execution on target platform.

Transaction Level Models (TLMs) are being increasingly used by multi-core system designers for design validation and embedded SW development. However, with well defined modeling semantics and TLM automation tools, it is also possible to use TLMs for multi-core design. This paper presents recent research in automatic generation of timed TLMs for early, yet reliable, evaluation of multi-core design decisions. The TLMs are automatically generated from a given mapping of a concurrent application to a multi-core platform. The application code is annotated with delays at the basic-block level of granularity. Similarly, the platform services, such as communication and scheduling, also include timing delays. The TLM automation methods have been implemented in the embedded system environment (ESE) toolset. Our experimental results with ESE demonstrate that multi-core TLMs can be generated in the order of seconds; they simulate close to host-compiled application execution speed, and are more than 90% accurate compared to board measurements on average for industrial size examples. Therefore, TLM automation enables early and reliable evaluation of multi-core design decisions.

In this paper, we present an accurate timed RTOS model within transaction level models (TLMs). Our RTOS model, implemented on top of system level design language (SLDL), incorporates two key features: RTOS behavior model and RTOS overhead model. The RTOS behavior model provides dynamic scheduling, inter-process communication (IPC), and external communication for timing annotated user applications. While the RTOS behavior model is running, all RTOS events, such as context switch and interrupt handling, are passed to RTOS over-head model to adopt the overhead during system execution. Our RTOS overhead model has processor- and RTOS-specific pre-characterized overhead information to provide cycle approximate estimation. We demonstrate the applicability of our model using a multi-core platform executing a JPEG encoder. Experimental results show that the proposed RTOS model provides the high accuracy, 7% off compared to on-board measurements while simulating at speeds close to the reference C code.

This paper presents synthesis of hardware dependent software (HdS) for multicore and many-core designs using embedded system environment (ESE). ESE is a tool set, developed at UC Irvine, for transaction level design of multicore embedded systems. HdS synthesis is a key component of ESE back-end design flow. We follow a design process that starts with an application model consisting of C processes communicating via abstract message passing channels. The application model is mapped to a platform net-list of SW and HW cores, buses and buffers. A high speed transaction level model (TLM) is generated to validate abstract communication between processes mapped to different cores. The TLM is further refined into a pin-cycle accurate model (PCAM) for board implementation. The PCAM includes C code for all the HdS layers including routing, packeting, synchronization and bus transfer. The generated HdS methods provide a library of application level services to the C processes on individual SW cores. Therefore, the application developer does not need to write low level HdS for board implementation. Synthesis results for an multi-core MP3 decoder design, using ESE, show that the HdS is generated in order of seconds, compared to hours of manual coding. The quality of synthesized code is comparable to manually written code in terms of performance and code size.

This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multi-core designs. The inputs are application C processes and their mapping to processing units in the platform. The processing unit model consists of pipelined datapath, memory hierarchy and branch delay model. Using the processing unit model, the basic blocks in the C processes are analyzed and annotated with estimated delays. This is followed by a code generation phase where delay-annotated C code is generated and linked with a SystemC wrapper consisting of inter-process communication channels. The generated TLM is compiled and executed natively on the host machine. Our key contribution is that the estimation technique is close to cycle-accurate, it can be applied to any multi-core platform and it produces high-speed native compiled TLMs. For experiments, timed TLMs for industrial scale designs such as MP3 decoder were automatically generated for 4 heterogeneous multi-processor platforms with up to 5 PEs under 1 minute. Each TLM simulated under 1 second, compared to 3-4 hrs of instruction set simulation (ISS) and 15-18 hrs of RTL simulation. Comparison to on-board measurement showed only 8 % error on average in estimated number of cycles.

This paper presents a tool for automatic generation of transaction level models (TLMs) in SystemC for MPSoC designs with custom communication platforms. The MPSoC platform is captured as a graphical net-list of components, busses and bridge elements. The application is captured as C processes mapped to the platform components. Once the platform is decided, a set of transaction level communication APIs is automatically generated for each application C process. After the C code is input, an executable SystemC TLM of the design is automatically generated using our tool. This TLM can be executed using standard SystemC simulators for early functional verification of the design. Although, several TLM styles and standards have been proposed in the past, our approach differs in the fact that the designers do not need to understand the underlying SystemC code or TLM modeling style to verify that their application executes on the selected platform. Another key advantage of our tool is that the platform can be easily customized for the application and a new TLM for that platform can be automatically generated. The TLM can be used to program the custom platform early in the design cycle before the components are available. Our experimental results demonstrate that for large industrial applications such as MP3 decoder and H.264, high-speed TLMs can be generated for several platforms in a few seconds.

This paper presents a tool for automatic synthesis of RTL interfaces for heterogeneous MPSoC from transaction level models (TLMs). The tool captures the communication parameters in the platform and generates interface modules called universal bridges between buses in the design. The design and configuration of the bridges depend on several platform components including heterogeneity of the components, traffic on the bus, size of messages and so on. We define these parameters and show how the synthesizable RTL code for the bridge can be automatically derived based on these parameters. We use industrial strength design drivers such as an MP3 decoder to test our automatically generated bridges for a variety of platforms and compare them to manually designed bridges on different quality metrics. Our experimental results show that performance of automatically generated bridges are within 5% of manual design for simple platforms but surpasses them for more complex platforms. The area and RTL code size is consistently better than manual design while giving 5 orders of improvement in development time.

This paper addresses the problem of long design cycle of MPSoCs communication SW with automatic synthesis. The tool we propose takes as input a transaction level model (TLM) of MPSoC communication and outputs pin and cycle-accurate (PCA) bus drivers that can be linked to the synthesizable PCA model (PCAM).

Communication between components, with different interface protocols, requires an extra component that must translate one protocol to another. This component is referred to as a transducer. In this paper we describe the design and implementation of a transducer between AMBA bus and TMS DSP bus. The transducer allows system designers to send data from AMBA compliant components to TMS compliant ones, and vice versa. The transducer was modeled in Verilog and implemented on Xilinx VirtexII FPGA board

With the rise in complexity of modern systems, designers are spending a significant time on modeling at the system level of abstraction. This paper introduces Model Algebra, a formalism built on top of system level design languages, that can be used for implementing functionality preserving transformations on system level models. Such transformations enable us to implement high level design decisions without having to write new models for each design decision. Moreover, since these transformations preserve functionality, the transformed models do not need to be re-verified. We present the definition of Model Algebra and show how system level models can be represented as expressions in this formalism. The laws of Model Algebra are use to define correct model transformations. We show a system level design scenario, where design decisions gradually refine the functional model of the system to an architectural model with components and communication structure. The refinement can be performed using the correct model transformations in our formalism.

In this paper we present a scheme for reducing the amount of synchronization overhead needed between components, after HW/SW partitioning, to preserve the original control flow of the specification. Since traffic between components is expensive, our scheme can significantly enhance the performance of the system implementation. Our optimization technique dynamically groups the tasks in the specification such that synchronization for different tasks can be shared. The grouping depends on the partitioning decision, and hence, is performed during the generation of the partitioned model. We apply our grouping algorithm for various partitions on system level models of industry standard designs. The experimental results show significant reduction in synchronization overhead compared to the unoptimized model.

Increase in system level modeling has given rise to a need for efficient functional validation of models above cycle accurate level. This paper presents a technique for comparing system level models, before and after the static scheduling of tasks on processing elements of the architecture. We derive a graph representation from models written in system level design languages (SLDLs) and define their execution semantics. The notion of functional equivalence of system level models is established using these graphs. We then present well defined rules for reduction of such graphs to a normal form. Finally, we show how to check for functional equivalence of two system level models by isomorphism of their normal graph representations. A checker built on the above concept is used to automatically validate the functional correctness of the static scheduling step. As a result, the models generated for various scheduling decisions do not have to be reverified using costly simulations.

This paper presents an algorithm for automatic generation of an architecture model from a functional specification, and proves its correctness. The architecture model is generated by distributing the intended system functionality over various components in the platform architecture. We then define simple transformations that preserve the execution semantics of system level models. Finally, the model generation algorithm is proved correct using our transformations. As a result, we have an automated path from a functional model of the system to an architectural one and we need to debug and verify only the functional specification model, which is smaller and simpler than the architecture model. Our experimental results show significant savings in both the modeling and the validation effort.

This paper presents a methodology and algorithms for automatic communication refinement. The communication refinement task in system-level synthesis transforms abstract data-transfer between components to its actual bus level implementation. The input model of the communication refinement is a set of concurrently executing components, communicating with each other through abstract communication channels. The refined model reflects the actual communication architecture. Choosing a good communication architecture in system level designs requires sufficient exploration through evaluation of various architectures. However, this would not be possible with manually refining the system model for each communication architecture. For one, manual refinement is tedious and error-prone. Secondly, it wastes substantial amount of precious designer time. We solve this problem with automatic model refinement. We also present a set of experimental results to demonstrate how the proposed approach works on a typical system level design.