In this paper, we propose a triple-mode baseband (BB) receiver (RX) architecture for cyclic prefix orthogonal frequency division multiplexing (CP-OFDM) with weighted overlap and add (WOLA) technique. The system specifications follow the IEEE 802.11ad/ay standard for next-generation millimeter wave communications. This BBRX is a flexible and expandable architecture due to the modularized, parameterized, and feed-forward data flow design strategies. The non-ideal circuit effects, such as frequency offset, phase noise, power amplifier (PA) non-linearity, and adjacent channel interference are jointly considered for the overall performance evaluation. The simulation results show that CP-OFDM with WOLA (W-CP-OFDM) and filter bank multicarrier (FBMC) present similar out-of-band performance while considering PA non-linearity. The synthesis results indicate that the W-CP-OFDM/FBMC has 2.1%/97% gate count increased overhead as compared to CP-OFDM.

In this paper, we design a power amplifier (PA) digital pre-distortion (DPD) module at the baseband transmitter to pre-compensate the nonlinearity and memory effect of the PA. In terms of DPD, we propose a low-complexity pseudo direct learning (PDL) DPD architecture based on the system level point of view according to the IEEE 802.11ad/ay specifications. The compensated error vector magnitude (EVM) performance of nonlinearity and memory effects can be improved from -12.8 dB to -21.7 dB at 16-QAM mode. The gain flatness of the -3 dB bandwidth can be extended from 0.3$\pi$ to 0.78$\pi$ with improving of 2.6 times. For the hardware implementation, we use TSMC 28-nm HPC_PLUS CMOS technology with four times parallelism to achieve 2.5 GHz chip rate. The gate counts and power of the proposed DPD design are 273.1 K and 98.0 mW, respectively.

Millimeter-wave (mmWave) RF and analog front-end circuits are very susceptible to chip process and temperature variation, which cause I/Q mismatch and DC offset. As a consequence, the system performance can be seriously degraded, especially in wideband multi-Gb/s systems. This paper proposes an online estimation and compensation in the baseband receiver end of a single carrier (SC) system for TX and RX frequency independent (FI) initial and time-varying (TV) I/Q mismatch and DC-offset. Based on specification of IEEE 802.11ay, the compensated image rejection ratio (IRR) performance of the TX and RX FI I/Q mismatch effects can be improved from 16.43 dB to 54.70 dB at SNR of 25.52 dB. Moreover, we propose a novel algorithm based on the Golay sequence for estimation and compensation to cancel TX and RX initial/TV DC-offset. The DC-offset in the I/Q channel is improved from −56.46 dB/−58.56 dB to −97.30 dB/−98.70 dB at SNR of 25.52 dB. In the hardware implementation, a four-time parallelism architecture are proposed to work at a 625 MHz clock rate with a 28-nm HPC_PLUS CMOS process under 64-QAM mode for 15 Gbps transmission. Using a clock gating control scheme for FI I/Q mismatch and DC-offset estimator, the total power of the proposed the module can be reduced from 59.5 mW to 32.7 mW. The gate count and power of the proposed estimation/compensation design are only 2.94% and 1.69% of the overall digital RX baseband gate count and power consumption.

This article proposes a digital two-stage phase noise (PN) compensation and residual carrier frequency offset (rCFO) and residual sampling clock offset (rSCO) tracking module in the baseband receiver side for single carrier (SC) systems in the millimeter-wave (mmW) band. The proposed two-stage PN compensation and rCFO/rSCO tracking module (2STG-PNC&T) includes a correlation-based linear interpolation method for the common phase error (CPE) of the low-frequency PN, a subsymbol CPE compensation with a reformed low-complexity π/4robust PN slicer for the high-frequency PN, and a tracking mechanism for rCFO and rSCO estimation on 64-QAM under the harsh PN condition of the frequency synthesizers used in the mmW band. The proposed module can restrict the maximum rCFO/rSCO within ±0.4 ppm and track the phase error caused by the PN successfully. Besides, the compensated power spectral density of the residual PN is reduced from -90 to -125 dBc/Hz at 1-MHz offset. A four-time parallelism architecture of the new 2STG-PNC&T is proposed to work at a 625-MHz clock rate under 64-QAM for 15 Gb/s transmission. The gate count/power of the proposed design is only 4.0%/6.9% of the overall digital baseband, respectively.

In this paper, we propose a self-healing technique with the smart sensing capability to exactly estimate and pre-compensate both the imperfect effects of IQ mismatch and LO leakage of the up-conversion mixer under the non-flat path impulse response (PIR) for improving TX EVM in 60 GHz broadband wireless communication systems. The proposed method may use the direct digital frequency synthesis (DDFS) module to send the test signals including a single-tone (ST) and a two-tone (TT) modes for sensing PIR and estimating the imperfect effects of the up-conversion mixer, respectively. The 8-bit fixed-point simulation result shows the proposed technique can achieve very excellent results.

In this paper, we proposed an all-digital self-interference cancellation (DSIC) with correction vector for convolution (CVC) technique to eliminate serious multipath self-interference for orthogonal frequency-division multiplexing (OFDM) full-duplex transmission in 60 GHz band. The CVC can solve the non-equivalence of circular and linear convolution. This work based on IEEE 802.15.3c/IEEE 802.11ad specification is synthesized with 40 nm 1P9M general purposes process. Under the Access Point (AP) and the User Equipment (UE) horn antennas being aligned face to face, the 9-bit fixed-point simulation result shows the proposed technique can achieve the target of the uncoded bit-error-rate (BER) of 10-2at signal-to-noise ratio (SNR) of 24.8 dB satisfying the requirement of 26 dB.

In this paper, we propose a tracking mechanism for the residual sampling clocking offset (SCO) with corresponding pilot and auxiliary pilot arrangements for filter bank multi-carrier (FBMC) offset QAM (OQAM) baseband receiver in the 60 GHz band. This work can effectively compensate the non-ideal effects on the high-band subcarriers while using more data subcarrier for increasing bandwidth efficiency. This work is designed based on IEEE 802.15.3c and IEEE 802.11ad standards and synthesized with 40 nm 1P9M general purposes (GP) process. The proposed SCO tracking module with the proposed alternated pilot and auxiliary pilot arrangement can improve the BER floor and reach to 10−2 at SNR of 22 dB which is only 1.75 dB more than that of no SCO effect in 64-QAM modulation.

In this paper, a novel memory access reordering polyphase network (PPN) for 60 GHz filter bank multi-carrier (FBMC) offset QAM (OQAM) baseband receiver is presented. The 8X-parallelism architecture of PPN is integrated into our 8X-parallelism digital baseband receiver. The PPN is designed based on IEEE 802.15.3c and IEEE 802.11ad standards. The PPN contains three key modules including memory bank, filter coefficient selector and 4-tap PPN filter. The proposed PPN is synthesized with 40 nm 1P9M general purposes (GP) process. The implementation result shows it can operate at specified 330/500 MHz clock rate with power consumption of 17/26 mW at 0.81 V supply voltage. With 8X-parallelism architecture, the sampling rate supports up to 2.64/4 GHz.