Small quantized neural networks with strong requirements on throughput and latency can be translated into logic circuits and synthesized by logic design tools. With networks having no state (memory), the circuits are combinational. To capture the function of the network (or a part of it) as a logic function, two approaches have been taken. The first one observes the inputs and outputs, while the network predicts a training set, and uses them directly as specification. The response to activation values that have not occurred in the training set remains unspecified. The other approach uses a complete set of activation values at the input of the examined part. We measured accuracy, the influence of logic minimization, and their impact on the final synthesized circuit on dense neural networks in different stages of low-magnitude pruning on the MNIST and JSC datasets. The results show that the first method can be used for functions with fan-in below 10–12 while not working against generalization. We also document the quantitative changes in quantized networks.

Neural networks with quantized activation functions cannot adapt the quantization at the input of their first layer. Preprocessing is therefore required to adapt the range of input data to the quantization range. Such preprocessing usually includes an activation-wise linear transformation and is steered by the properties of the training set. We suggest to include the linear transform into the training process. Using the Jet Stream Classification task and an evaluation architecture of three quantized dense layers, we document that it improves accuracy, requires the same resources as standard preprocessing, plays a role in network pruning, and is reasonably stable with respect to initialization.

In digital circuit testing, output response compaction can have a significant impact on fault coverage. The loss of fault coverage is caused by aliasing in the output response compaction. Classical approaches to reducing (eliminating) fault aliasing are based on modifications of the compactor design or modifying precomputed test sequence. In this paper, we propose a completely different approach based on a dedicated test pattern generation algorithm. The algorithm generates a test sequence with minimal aliasing for targeted faults. As the generated test sequence is tailored to given static and dynamic compactor structures, any response compactor can be used without a change in the design. We expand on our previous work, zero-aliasing ATPG, and incorporate pseudo-Boolean optimization techniques in the process.The algorithm is evaluated using an LFSR-based MISR on a selection of benchmark circuits. A comparison with a state-of-the-art ATPG process without anti-aliasing measures is drawn.

Physical attacks, namely invasive, observation and combined, represent a great challenge for today's digital design. Successful class of strategies adopted by industry, allowing hiding data dependency of the side channel emissions in CMOS is based on balancing. Although attacks on CMOS dynamic power represent a class of state-of-the-art attacks, vulnerabilities exploiting data dependency in CMOS static power and light- modulated static power were recently presented. In this paper, we describe structures and techniques developed to enhance and balance traditional static CMOS bulk structures. To enable data dependency hiding, we propose low-level techniques based on complementary-value induced balancing currents, constant current source behavioral approximation, and light-sensing capability of traditional CMOS structures. The proposed techniques may be used to build a dual-rail circuit balanced from both perspectives: static and dynamic power. The publicly available TSMC180nm node standard cell simulation is used for evaluation.

The security of many digital devices strongly depends on a secret value stored in them. To mitigate security threats, high protection of such a value must be provided. Many attacks against (cryptographic) hardware as well as attack countermeasures were presented recently. As new attacks are invented continuously, it is important to analyze even potential threats to mitigate device vulnerability during its lifetime. In this paper, we report a novel voter-related vulnerability, which can be potentially misused to compromise the secret value stored in an embedded device.

The dummy rounds protection scheme, intended to offer resistance against Side Channel Attacks to Feistel and SP ciphers, has been introduced in earlier work. Its experimental evaluation revealed weaknesses, most notably in the first and last round. In this contribution, we show that the situation can be greatly improved by controlling the transition probabilities in the state space of the algorithm. We derived necessary and sufficient conditions for the round execution probabilities to be uniform and hence the minimum possible. The optimum trajectories over the state space are regular and easy to implement.

As digital devices penetrate to many areas important for the present society, it is important to analyze even potential threats to mitigate vulnerabilities during their lifetime. In this paper, we analyze the data dependency of the photocurrent induced by a laser beam in the illuminated CMOS circuit. The data dependency may introduce potential threat(s) originating in the nature of the CMOS technology. The data dependency can be potentially misused to compromise the data processed by an embedded device. We show that also the devices employing dual-rail encoding to hide data-dependency are not safe.

While political commitments for building exascale systems have been made, turning these systems into platforms for a wide range of exascale applications faces several technical, organisational and skills-related challenges. The key technical challenges are related to the availability of data. While the first exascale machines are likely to be built within a single site, the input data is in many cases impossible to store within a single site. Alongside handling of extreme-large amount of data, the exascale system has to process data from different sources, support accelerated computing, handle high volume of requests per day, minimize the size of data flows, and be extensible in terms of continuously increasing data as well as increase in parallel requests being sent. These technical challenges are addressed by the general reference exascale architecture. It is divided into three main blocks: virtualization layer, distributed virtual file system, and manager of computing resources. Its main property is modularity which is achieved by containerization at two levels: 1) application containers - containerization of scientific workflows, 2) micro-infrastructure - containerization of extreme-large data service-oriented infrastructure. The paper also presents an instantiation of the reference architecture - the architecture of the PROCESS project (PROviding Computing solutions for ExaScale ChallengeS) and discuss its relation to the reference exascale architecture. The PROCESS architecture has been used as an exascale platform within various exascale pilot applications. This work will present the requirements and the derived architecture as well as the 5 use cases pilots that it made possible.

Global trends such as mass customization and lot size one, demand flexibility, autonomy and adaptability in production. Interoperability of devices is a key challenge as production systems evolve into Cyber-Physical Production Systems (CPPS). As part of the German strategic project Industrie 4.0 (I4.0), concepts and solutions for continuous digitization of production are being developed, in order to meet these numerous challenges. The concept of the Asset Administration Shell (AAS) was introduced in order to provide data and information in a standardized and semantically described manner, thus enabling interoperability and easy interaction. In this paper, we show how users can translate a semantic description of plants, machines or individual components that are based on a standardized Open Platform Communication Unified Architecture (OPC UA) information model, into the AAS information model.

The rising amount of data in Internet of Things (IoT) and Wireless Sensor Network (WSN) scenarios motivates new computing paradigms like fog or edge computing. To reduce the amount of data sent upstream, in-network (pre-)processing is widely used, which demands for both compute and distributed storage capacities in highly constrained environments.

This paper describes the technique of Dummy Rounds as a countermeasure against DPA in hardware implementation of round-based ciphers. Its principle is inspired by several well-known countermeasures used in hardware as Hiding and Dynamic Reconfiguration as well as countermeasures used in software implementations as Dummy cycles, Random order execution or Hiding in time. Being inspired by countermeasures based on dynamic reconfiguration, this method combines hiding of power consumption with hiding in time. In this work we also discuss the amount of randomness available for the control of the computation.

This paper follows recent research on insufficient synthesis performance for XOR-intensive circuits, and introduces a novel logic representation with a native support of XOR gates, the XOR-AND-Inverter Graphs (XAIGs). A rewriting algorithm over XAIG has been implemented in the logic synthesis and optimization package ABC, as the first step towards a complete synthesis process. The results show that XAIG based rewriting can help to discover XORs and improves the area of a mapped network in some cases.

This paper presents a method for generating optimum multi-level implementations of Boolean functions. It is based on Satisfiability (SAT) problem solving, while different SAT techniques are employed to reach different targets. The method is able to generate one, or enumerate all optimum implementations, while any technology constraints can be applied. Results for 4 input functions implemented by XOR AND-Inverter-Graphs (XAIGs) with different XOR nodes costs are presented. Scalability and feasibility of the method is presented. Finally, an experimental evaluation of XAIG based rewriting algorithm with optimum replacement circuits is presented and compared with the previous solution.

Aliasing in the test response compaction is an important source of fault coverage loss. Methods to avoid the aliasing generally require modification of the compactor to some extent. This can lead to a higher compactor complexity and consequently to higher area overhead, longer signal propagation delays, etc.We propose a novel method, the Zero-aliasing ATPG (ZATPG), which is able to reduce the aliasing without need of designing new compactors. ZATPG works by augmenting the SAT-based ATPG process to constrain test pattern generation to produce no aliasing in the compactor. The method is general enough to be applicable to any compactor design.We demonstrate our method on a LFSR-based MISR compactors, using the Single Stuck-At fault model. Our method is able to find a test with zero aliasing and complete fault coverage for smaller compactors than conventional, unguided ATPG. Thus, the area overhead of the compactor can be reduced, while the complete fault coverage is preserved.

The method proposed in this paper allows to construct error-correcting systems by combining time and area redundancy. In such a system, error detection is performed online, while error correction uses a short-duration offline test. The time penalty caused by the offline test applies only when an error is detected. The error-correcting ability in such a system is comparable with TMR, the area overhead is smaller for a class of circuits, and the delay penalty caused by the offline test remains reasonably small. The short-duration offline test is possible only when extensive design-for-test practices are used. Therefore, a novel gate structure is presented, which allows to construct combinational circuits testable by a short-duration offline test. The proposed test offers complete fault coverage with respect to the stuck-on and stuck-open fault model.

In this work we present a novel fault-tolerant circuits design method. It combines time and area redundancy to achieve error-correction abilities similar to a triple-modular redundancy (TMR) and the area-overhead close to a duplex system. New logic gates design allowing a complete stuck-at fault testability will be presented. Our method allows to test combinational parts of the circuit using a universal short-duration offline test. The offline-testable module with an online-checker allows to compose a fault-tolerant system with the mentioned properties. This system will be denoted as a time-extended duplex scheme. In this scheme the offline test is sufficiently short to allow error correction during the computation (paused pipeline). The presented method adopts some principles from dual-rail logic and asynchronous circuits design.

In this paper we present an experimental analysis of robustness of Electronic Design Automation (EDA) tools, with respect to different seemingly unimportant aspects (bias) introduced by the designer, “from outside”. The algorithms employed in EDA tools should be immune to these completely, since such aspects do not carry any useful information - source files differing in these aspects are semantically equivalent. However, we show that most of the studied tools are seriously sensitive here, much more than ever reported. The results indicate, that experiments conducted to evaluate the performance of EDA tools must take such behavior into consideration. Also the notion of a benchmark is questioned.

This paper presents a novel ATPG and test compression algorithm based on Pseudo-Boolean (PBO) optimization. Similarly to SAT-based ATPGs, the test for each fault is represented implicitly as a PBO instance. The optimization process solves the problem of maximizing the number of unspecified values in the test. A novel don't care aware circuit-to-PBO conversion procedure is presented. The obtained unspecified values in the test are efficiently exploited in test compression. The produced compressed test sequence is suited for the RESPIN decompression architecture, thus for testing systems on-chip. The presented experimental results show the efficiency and competitiveness of the proposed method.

It is known that EDA tools produce results of different quality dependent on seemingly neutral details in the input. We bring further results in this direction, which show that the differences can impair any quantitative comparisons of the tools. To gain qualitative insight, we present a stochastic model of result quality based on Gaussian Mixtures. We show on three case studies how these models help to evaluate and improve EDA algorithms.

This paper presents a novel ATPG algorithm directly producing compressed test patterns. It benefits both from the features of satisfiability-based techniques and symbolic simulation. The ATPG is targeted to architectures comprised of interconnected embedded cores, particularly to the RESPIN architecture. We show experimentally that the proposed ATPG significantly outperforms the state-of-the-art approaches in terms of the test compression ratio.

We present a method of improving the iterative power of resynthesis of Boolean networks in this paper. In principle it is based on iterative resynthesis of parts of the network, instead of processing the network as a whole. The parts are randomly selected, thus more variability is introduced. The process is scalable, at least as much as the state-of-the-art. We show that our method performs better than the academic state-of-the-art, the ABC tool from Berkeley. This is documented by extensive experiments on LGSynth'93 benchmark circuits.

Circuits which are designed to be dependable are evaluated after gate-level design. To demonstrate the influence of implementation technology on dependability parameters, we developed a simple method which transforms the evaluation problem into conceptual hardware and then to SAT instances and can accommodate any combinational fault model. The performed evaluation demonstrated that the dependability parameters of the implementations correlate to a significant degree.

Testing of digital circuits seems to be a completely mastered part of the design flow, but constrained test patterns generation is still a highly evolving branch of digital circuit testing. Our previous research on constrained test pattern generation proved that we can benefit from an implicit representation of test patterns set in CNF (Conjunctive Normal Form). Some techniques of speeding up the constrained SAT-based test patterns generation are described and closely analyzed in this paper. These techniques are experimentally evaluated on a real SAT-based algorithm performing a constrained test patterns compression based on overlapping of test patterns. Experiments are performed on a subset of ISCAS'85 and '89 benchmark circuits. Results of the experiments are discussed and recommendations for a further development of similar SAT-based tools for constrained test patterns generation are given.

Recently, it has been shown that synthesis of some circuits is quite difficult for conventional methods. In this paper we present a method of minimization of multi-level logic networks which can solve these difficult circuit instances. The synthesis problem is transformed on the search problem. A search algorithm called Cartesian genetic programming (CGP) is applied to synthesize various difficult circuits. Conventional circuit synthesis usually fails for these difficult circuits; specific synthesis processes must be employed to obtain satisfactory results. We have found that CGP is able to implicitly discover new efficient circuit structures. Thus, it is able to optimize circuits universally, regardless their structure. The circuit optimization by CGP has been found especially efficient when applied to circuits already optimized by a conventional synthesis. The total runtime is reduced, while the result quality is improved further more.

In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method is targeted to systems on chip (SoCs)provided with the P1500 test standard. The RESPIN architecture can be used for test patterns decompression. The main idea is based on finding the best overlap of test patterns during the test generation, unlike other methods, which are based on efficient overlapping of pre-generated test patterns. The proposed algorithm takes advantage of an implicit test representation as SAT problem instances. The results of test patterns compression obtained for standard ISCAS'85 and `89benchmark circuits are shown and compared with competitive test compression methods.

We present experiments with synthesis tools using examples which are currently believed to be very hard, namely the LEKU examples by Cong and Minkovich and parity examples of our construction. In both cases, we found a way to produce reasonable results with existing tools. We identify the abilities that are crucial for achieving such results, and also generalize them to avoid similar cases of poor performance in future tools. I. INTRODUCTION Logic synthesis is believed to be a matured process, giving results reasonably close to optimum. Yet, there are still circuits which are very hard for any synthesis process. Cong and Minkovich (1) published a method for the construction of combinational circuits with known optimal implementa- tion (LEKO) or with known upper bound (LEKU). Here we study the latter ones, as the gap between the upper bound and obtained results are the largest. Our parity examples (2) are another case of difficult circuits. Synthesis tools give results an order or two bigger than a known upper bound. We investigated the reasons of the observed poor per- formance experimentally. We succeeded in finding tools and procedures that give satisfactory (i.e. not orders of magnitude worse) results, experimented further to obtain clues what makes those tools and procedures successful. First we describe our experimental methods. Secondly, ex- periments with both sets of examples are described together with the results obtained. Finally, we interpret the results and give requirements for future tools.

We present the architecture of digit-serial normal basis multiplier over GF(2m). The multiplier was derived from the multiplier of Agnew et al. Proposed multiplier is scalable by the digit width of general value in difference of the multiplier of Agnew et al. that may be scaled only by digit width that divides the degree m. This helps designers to trade area for speed e.g. in public-key cryptographic systems based on elliptic-curves, where m should be a prime number. Functionality of multiplier has been tested by simulation and implemented in Xilinx Virtex 4 FPGA.

We present two architectures of digit-serial normal basis multiplier over GF(2m). Proposed multipliers are scalable by the digit width of general value in difference of the multiplier of Agnew et al., that may be scaled only by digit width that divides the degree m. This helps designers to trade area for speed e.g. in cryptographic systems, where m should be a prime number. Functionality of multipliers has been tested by simulation and implemented in Xilinx Virtex 4 FPGA

Normal basis multipliers over GF(2m) with circular and linear structure are presented here. Proposed multipliers are scalable by the digit width of general value in difference of the multiplier of Agnew et al. that may be scaled only by digit width that divides the degree m. This capability enables designers to accelerate e.g. public-key cryptographic systems based on elliptic-curves, where m should be a prime number.