Power dissipation has become a critical design metric in microprocessor-based system design. In a multi-core system, running multiple applications, power and performance can be dynamically traded off using an integrated power management (PM) unit. This PM unit monitors the performance and power of each core and dynamically adjusts the individual voltages and frequencies in order to maximize system performance under a given power budget (usually set by the operating system). This paper presents a performance and power analysis methodology, featuring a simulation model for multi-core systems that can be easily reconfigured for different scenarios and a PM infrastructure for the exploration and analysis of PM algorithms. Two algorithms have been implemented: one for discrete and one for continuous power modes based on non-linear programming. Extensive experiments are reported, illustrating the effect of power management both at the core and the chip level.

System level design methodology and language support for high-level modeling enhances productivity for designing complex embedded systems. For an effective methodology, efficiency of simulation and a sound refinement-based implementation path are also necessary. Although some of the recent system level design languages (SLDLs) such as SystemC, SystemVerilog, or SpecC have features for system level abstractions, several essential ingredients are missing from these. We consider: 1) explicit support for multiple models of computation (MoCs) or heterogeneity so that distributed reactive embedded systems with hardware and software components can be easily modeled; 2) the ability to build complex behaviors by hierarchically composing simpler behaviors and the ability to distinguish between structural and heterogeneous behavioral hierarchy; and 3) hierarchical composition of behaviors that belong to distinct MoCs, as essential for successful SLDLs. One important requirement for such an SLDL should be that the simulation semantics are compositional, and hence no flattening of hierarchically composed behaviors are needed for simulation. In this paper, we show how we designed SystemC extensions to facilitates for heterogeneous behavioral hierarchy, compositional simulation semantics, and a simulation kernel that shows up to 40% more efficient than standard SystemC simulation

Enhancing productivity for designing complex embedded systems requires system level design methodology and language support for capturing complex design in high level models. For an effective methodology, efficiency of simulation and a sound refinement based implementation path are also necessary. Although some of the recent system level design languages for system level abstractions, several essential ingredients are missing from these. We consider (i) explicit support for multiple models of computation (MoCs) or heterogeneity; (ii) the ability to build complex behaviors by hierarchically composing simpler behaviors; and (iii) hierarchical composition of behaviors that belong to distinct models of computation, as essential for successful SLDLs. These render an SLDL with modeling fidelity that exploits both heterogeneity and hierarchy and allows for simpler modeling and efficient simulation. One important requirement for such an SLDL should be that the simulation semantics be also compositional, and hence no flattening of hierarchically composed behaviors be needed for simulation. In this paper we show how we designed SystemC extensions to provide facilities for heterogeneous behavioral hierarchy, compositional simulation semantics, and implemented a simulation kernel which we show experimentally as up to 50% more efficient than standard SystemC simulation

SystemC, users and tool providers are at a crossroads. More and more companies are using SystemC; however EDA companies are hesitant to give a full commitment to SystemC tools, especially at system-level. There are several reasons for this dichotomy. While users seem excited about SystemC for its technical qualities for system-level design, tool providers may not share this excitement because of the current small market for such tools. Are the existing (free) reference implementation and the current small market for system level tools to blame, or are there any technical issues impeding the fast development of SystemC tools? Among the SystemC users from industry and academia there is currently some uncertainty about the future availability of state of the art EDA tools supporting SystemC. This panel brings together industrial SystemC users as well as EDA companies to discuss these issues. The industrial panellists will present the current situation regarding the use of SystemC in industry, its importance (or lack thereof) for system design and future needs for such tools. The tool providers will explain their current position regarding the commitment to SystemC and clarify their future plans for supporting it.

This panel will bring six speakers relating their success stories about design starting at the system-level. The format is an educational Panel aimed at informing DAC attendees of the challenges (difficulties and pitfalls) and opportunities (sizable benefits and lessons learned from these experiences).

Early power analysis for systems-on-chip (SoC) is crucial for determining the appropriate packaging and cost. This early analysis commonly relies on evaluating power formulas for all cores for multiple configurations of voltage, frequency, technology and application parameters, which is a tedious and error-prone process. This work presents a methodology and algorithms for automating the power analysis of SoCs. Given the power state machines for individual cores, this work defines the product power state machine for the whole SoC and uses formal symbolic simulation algorithms for traversing and computing the minimum and maximum power dissipated by sets of power states in the SoC.

We describe the customizable control processor (CCP) platform based on PowerPC/spl reg/ 440 processor with a target frequency of 533 MHz as well as its design methodology. The hardened region of the chip contains cores and features found in many control and communications applications. The custom area of the chip allows for each application of CCP to be personalized with cores from the IBM core library or with unique logic implemented in IBM ASIC standard cell. A predefined logic template (customer logic file) with a set of standard CoreConnect/spl reg/ ports can be personalized with any function that can be implemented in the IBM ASIC technology. The customer logic file is synthesized placed and wired in the custom area of the chip. The custom area of the chip could be configured with approximately 2 M gates of logic. With all mask levels being personalized other configurations could include SRAM, and embedded DRAM incorporated in the custom logic. There are around 263 pre-assigned I/O for the hardened portion of the chip as well as around 177 I/O sockets available in the custom region to personalize. The CCP provides a flexible platform and design environment that effectively reduces the design effort, design time, and the design cost of systems on chip.

The exploding complexity of new chips and the ever decreasing time-to-market window are forcing fundamental changes in the way systems are designed. The advent of Systems-on-Chip (SoC) based on pre-designed intellectual-property (IP) cores has become an absolute necessity for embedded systems companies to remain competitive. Designing an SoC, however, is extremely complex, as it encompasses a range of difficult problems in hardware and software design. This paper explains a wide range of SoC issues including market drivers and trends, technology and integration aspects, early architecture definition, methodology, hardware and software design and verification techniques.

High-level synthesis operates on internal models known as control/data flow graphs (CDFG) and produces a register-transfer-level (RTL) model of the hardware implementation for a given schedule. For high-level synthesis to be efficient, it has to estimate the effect that a given algorithmic decision (e.g., scheduling, allocation) will have on the final hardware implementation (after logic synthesis). The main problem in evaluating this effect is that the CDFGs are very distinct from the RTL/gate-level models used by logic synthesis. This makes it impossible to estimate hardware costs accurately. Moreover, the fact that high-level and logic synthesis operate on different internal models precludes on-the-fly interactions between these tools. This paper presents a solution to these problems consisting of a novel internal model for synthesis which spans the domains of high-level and logic synthesis. This model is an RTL/gate-level network capable of representing all possible schedules that a given behavior may assume. This representation allows high-level synthesis algorithms to be formulated as logic transformations and effectively interleaved with logic synthesis.

Leading-edge systems-on-chip (SoC) being designed today could reach 20 Million gates and 0.5 to 1 GHz operating frequency. In order to implement such systems, designers are increasingly relying on reuse of Intellectual property (IP) blocks. Since IP blocks are pre-designed and pre-verified, the designer can concentrate on the complete system without having to worry about the correctness or performance of the individual components. That is the goal, in theory. In practice, assembling on SoC using IP blocks is still an error-prone, labor-intensive and time-consuming process. This paper discusses the main challenges in SoC designs using IP blocks and elaborates on the methodology and tools being put in place at IBM for addressing the problem. It explains IBM's SoC architecture and gives algorithmic details on the high-level tools being developed for SoC design.

Article Behavioral network graph: unifying the domains of high-level and logic synthesis Share on Author: Reinaldo A. Bergamaschi IBM T. J. Watson Research Center, NY IBM T. J. Watson Research Center, NYView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 213–218https://doi.org/10.1145/309847.309916Published:01 June 1999 12citation264DownloadsMetricsTotal Citations12Total Downloads264Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

The use of arrays and records in modern hardware-description languages (HDL) allows designs to be modeled at very high levels of abstraction. However, the support for these complex data types in current synthesis tools is very limited. This paper presents a comprehensive scheme to synthesize aggregate data types such as arrays and records, in a very general manner. The approach consists of mapping objects (variables and signals) of aggregate data types onto one-dimensional vectors, and generating specialized addressing/decoding hardware to be able to access any field of the data type. Arrays of multiple dimensions and any level of nesting of arrays and records are supported. This paper describes the whole process, from the language specification to the actual hardware structures created by synthesis.

The effective use of don't cares requires solving several theoretical and practical problems. The theoretical problems are caused by a need to have all tools in a methodology use a consistent semantics of don't cares, so as to guarantee correctness of the final implementation. Several common meanings of "don't care" will be considered, and their respective conditions for design correctness will be derived. The main theoretical result shows that in existing design languages, the following three desirable properties are mutually inconsistent: unrestricted use of non-Boolean values (e.g., X), implementing a large design one partition at a time, and assurance of correctness of the final implementation. A practical solution to this problem involves several issues: specifying don't cares in a language description, deriving them during high-level synthesis, and optimizing logic in their presence. Experimental results showing the impact of don't cares on logic quality are presented.

Resource sharing is one of the main tasks in high-level synthesis, and although many algorithms have addressed the problem there are still several limitations which restrict the generality and applicability of current algorithms. Most clique-partitioning-based algorithms use local and inaccurate cost-functions which result in inefficient results. This paper presents algorithms for the resource sharing problem on registers and functional units, and shows how they overcome the limitations of existing algorithms. The main characteristics of this work are: interleaved register and functional unit merging in a global clique partitioning based framework, accurate merging cost estimation, accurate interconnect cost estimation, relative control cost taken into account and efficient false loop elimination. The results obtained show significant improvements in the delay of designs, while also minimizing area, specially for large designs with many sharing possibilities.

As high-level synthesis techniques gain acceptance among designers, it is important to be able to provide a robust system which can handle large designs in short execution times, producing high-quality results. Scheduling is one of the most complex tasks in high-level synthesis, and although many algorithms exist for solving the scheduling problem, it remains a main source of inefficiency by either not producing high-quality results, not taking into account realistic design requirements, or requiring unacceptable execution times. One of the main problems in scheduling is the dichotomy between control and data. Many algorithms to date have been able to provide scheduling solutions by looking only at either the data part or the control part of the design. This has been done in order to simplify the problem; however, it has resulted in many algorithms unable to handle efficiently large designs with complex control and data functionality. This paper presents algorithms for combining dataflow and control-flow techniques into a robust scheduling system. The main characteristics of this system are as follows: 1) it uses path-based techniques for efficient handling of control and mutual exclusiveness (for resource sharing), 2) it allows operation reordering and parallelism extraction within the context of path-based scheduling, 3) it contains a control partitioning algorithm for design space exploration as well as for reducing the number of control paths, and 4) it combines the above algorithms into an adaptive scheduling system which is capable of trading optimality for execution time on-the-fly. Results involving billions of paths are presented and analyzed.

This paper analyzes the impact that a high-level design methodology can have in the total design cycle. The main question being raised here is how much high-level design tools really help. For example, one can use a high-level tool to perform scheduling or generate a pipelined implementation of a for loop; and that may save a week in design time. But that alone does not decrease the months of simulation time that still must be performed in large designs. This paper discusses these issues and presents possible approaches for making high-level design tools more effective in the total design cycle.

This paper describes optimization techniques using don't-care conditions that span the domain of high-level and logic synthesis. The following three issues are discussed: (1) how to describe and extract don't-care conditions from high-level descriptions; (2) how to pass don't-care conditions from high-level to logic synthesis; and (3) how to optimize the logic using don't-care conditions. Efficient techniques are given for these three problems which allow the use of large don't-care sets. Results from several examples demonstrate that these techniques are very effective for both area and delay minimization.

It is commonly expected that any correct implementation can replace its specification inside a larger design without violating the correctness of the whole design. This property (called replaceability) is automatically satisfied in the absence of don't cares because "correctness" by definition implies that specification and implementation compute the identical function. However don't cares allow an implementation to compute a different function, and thus make it difficult to ensure replaceability. Whether this problem occurs depends on the exact meaning of "don't care" and the associated definition of "correctness". We will consider three meanings of "don't care" and for each give conditions under which correct implementations may replace their specifications.

High-level synthesis has been an active research field since the early eighties. However, apart from a few exceptions the technology has so far failed to make a smooth transition into the industrial environment. The main reasons are related more to the lack of an integrated methodology, including design entry, simulation, and synthesis, than to the quality of the synthesis algorithms. Experiences in applying the HIS system (High-level IBM Synthesis System) to real designs led to the development of a system and methodology which integrate language modeling, simulation, high-level, and logic synthesis. This paper presents the main concepts behind this system, namely, its modeling, synthesis, and simulation capabilities. Moreover, it addresses some of the problems encountered when transferring high-level synthesis to a production environment.>

A comprehensive timing model for behavioral-level specifications and algorithms for timing analysis in high-level synthesis is described. It is based on a timing network which models the data flow as well as the control flow in the behavioral input specification. The delay values for the network modules are created by invoking the same logic synthesis procedure applied after behavioral synthesis. The timing network is built only once for a given behavioral description. Several parameters are used to explore different scheduling possibilities as well as different optimization modes (area, delay), without changing the network. The use of the timing model in conjunction with a path-based scheduling algorithm is presented. Results for several benchmarks attested to the accuracy of this approach.>

A method and algorithms for exploring the design space between the register-transfer and behavioral levels are presented. The method consists of the specification of a high-level state machine, which combines the advantages of a specific control structure, by means of states and transitions, with the flexibility of behavioral descriptions inside each high-level state. High-level synthesis techniques are used for synthesizing this machine. As a result, the user has control over the final controller implementation and is able to perform high-level tradeoffs between control and data path.>

Article Data-path synthesis using path analysis Share on Authors: Reinaldo A. Bergamaschi IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, N.Y. IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, N.Y.View Profile , Raul Camposano IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, N.Y. IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, N.Y.View Profile , Michael Payer IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, N.Y. IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, N.Y.View Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 591–596https://doi.org/10.1145/127601.127738Published:01 June 1991 16citation237DownloadsMetricsTotal Citations16Total Downloads237Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

The author discusses the effects of false paths and their consequences in scheduling and allocation during high-level synthesis. False paths through the control-flow graph may occur due to sequences of conditional operations. The detection of false paths during scheduling may result in a smaller number of states, improved operator sharing, and smaller control logic. A heuristic algorithm is presented for the detection and elimination of false paths during path-based scheduling. Results for benchmark examples are presented. For the designs which contained false paths, the percentage of false paths varied from 5% to 83%. A reduction of 15% in the final cell count for one benchmark was obtained by eliminating false paths. Even though the proposed algorithm is heuristic and cannot guarantee the detection of all false paths, it did find all false paths in the small to medium size examples tried. In most cases the condition trees are small, with few data dependencies, which increases the probability of a false path being found by the algorithm.>

SKOL, a system for combinational logic synthesis using library of cells, with emphasis on technology mapping algorithms, is described. It combines current multilevel optimization techniques with a new approach to the technology mapping problem. This approach uses a numerical string for representing the Boolean expressions and the library cells, which allows a fast selection process. Technology mapping is performed directly on the factored Boolean network, without decomposing it into primitive gates. A dynamic programming approach is used for mapping the whole Boolean network based on the possible matches for each node. Results from benchmark examples show that this approach is effective in reducing the final cell count. Comparisons with existing systems are presented.>

Path-based scheduling algorithms consider all possible sequences of operations (called paths) in a control-flow graph. Unlike most scheduling techniques used in high-level synthesis, they stress optimization across conditional branches. This paper presents several path-based algorithms. An exact algorithm finds the minimum number of control steps required for each possible path being executed. Heuristic solutions were also implemented. Extensive application of these algorithms to the benchmarks of the High-Level Synthesis Workshop showed the practical feasibility of such methods.

SKOL, a system for the synthesis of combinational logic using a library of cells that emphasizes technology-mapping algorithms, is described. It combines current multilevel optimization techniques with a novel approach to technology mapping. Each factor (or the factorized Boolean equation) can be implemented by itself or collapsed into the higher level expression containing it, which is then implemented. An expression can be implemented in several ways, which differ in the degree of factorization. A number of selected implementations is evaluated and the one with minimal cost (area or delay) is chosen. The mapping algorithms are independent of the library of cells, which can be easily modified. Results from benchmark examples were better than or comparable to those for existing systems.>