In this research, we attempted to support the learning of the UML modeling skills and social skills required in software development scenarios as part of programming education in the Department of Engineering. We conducted a class based on PBL in which the learners formed teams to build a robot using LEGO Mindstorms. The results confirmed that through the classes, the learners showed improvements in both modeling skills and social skills. These results demonstrate the educational effectiveness of class design based on PBL and using the theme of building a robot, and the effectiveness of the modeling template created through this research.

This paper proposes a self-test method of dynamically reconfigurable processors (DRPs) without area overhead. This method constructs a test frame of processor elements (PEs) such that it consists of test pattern generators, response analyzers and PEs under test, and switches several test frames dynamically so as to test all the PEs. Since the number of contexts and test application time are subject to the structure of test frames, we design several test frames with different structures and discuss the relationship of the structures to the number of contexts and test application time. Based on this discussion, we can construct the best test frame according to a given test environment.

The authors propose an algorithm for automatically generating a mask pattern from the logical description of a large-scale CMOS circuit, i.e., 'macro', consisting of up to several thousands of transistors. The layout model considered is a 2-D or 'multi-row' model which is composed of a set of rows of paired PMOS and NMOS transistors. The large-scale layout synthesis is attained by combining an effective 1-D layout synthesis and a standard cell layout algorithm in divide-and-conquer style. For a practical circuit, the proposed algorithm yields an 18% smaller layout than the conventional standard cell approach.>

In this paper, we present a new approach for the one-dimensional gate assignment problem. The original minimization problem is transformed into a restricted problem, and then a new heuristic algorithm is applied to it. The solution obtained by the algorithm is interpreted as a solution for the original problem. The whole process of the approach has been implemented and tested with various examples. Experimental results show that our approach can approximately produce optimum solutions.

Automatic layout algorithms, placement and routing, for function blocks of CMOS gate arrays are presented.