In this paper, we present a comparison between two methods, the modified Loeffler algorithm (11 MUL and 29 ADD) and distributed arithmetic, to implement the DCT/IDCT algorithm for MPEG or H.26x video compression using VHDL description language. The implementation has been achieved on Altera Stratix EP1S10 FPGA which provides a dedicated DSP blocks required for common signal processing functions. A new solution based on this DSP blocks used to implement multipliers for the modified Loeffler algorithm in order to optimize speed and area

This paper presents a low pass sigma-delta modulator (/spl Sigma//spl Delta/) for Analog-to-Digital conversion which uses the switched-current technique. The growth of this technique is limited by the clock feedthrough which induces an error on the output signal value. In order to cancel the effect of this phenomena a new method based on a current feedback loop is used. The /spl Sigma//spl Delta/ modulator implemented is a conventional second order and the whole circuit is designed with fully differential current mode building blocks. The circuit, designed in 0.8 /spl mu/m AMS single poly CMOS process, shows 55 dB dynamic range at 2 MHz sampling rate with 8 kHz input frequency bandwidth.

In the above paper1 Fleishchhammer and Dortok present a measurement system to analyze the metastable state in synchronizer circuits. We present the specific measures which have to be taken in the design for such a system to get intrinsic characterization of circuits. We propose a measurement system based on the introduction of a new parameter of synchronizer circuits allowing an accurate characterization of the considered phenomenom. Some results are given concerning standard flip-flops.