Embedded technologies such as IoTs, connected cars or medical equipment are often executed in constrained environment with limited resources. The high demand of security makes cryptography essential. Moreover, the security must consider physical attacks as these objects are physically accessible and can be tampered with. Lightweight Cryptography (LWC) proposes interesting candidates for securing the communications in constrained environments. As many lightweight cryptographic algorithms have been proposed with closed architectures, the features of agility and genericity could be considered. Moreover, a high robustness against side-channel analysis (SCA) is required when the connected object executes sensitive applications or manipulates private data.In this work, we propose the use of Rotating SBox Masking (RSM) protection as a generic protection that would fit most lightweight block cipher, more specifically those using 4×4 substitution boxes. This protection is developed as an extension to the RISC-V ISA through the use of additional generic instructions. This specific instruction set was implemented on the VexRisc core processor and tested with a protected implementation of the PRESENT cipher. It is easily portable to most nibble-based LWC cipher types. The security analysis of this secure RISC-V processor showed that SCA were impossible with up to 1 million traces.

This study investigates a new side-channel leakage observed in the inner rounds of an unrolled hardware implementation of block ciphers in a chosen-input attack scenario. The side-channel leakage occurs in the first round and it can be observed in the later inner rounds because it arises from path activation bias caused by the difference between two consecutive inputs. Therefore, a new attack that exploits the leakage is possible even for unrolled implementations equipped with countermeasures (masking and/or deglitchers that separate the circuit in terms of glitch propagation) in the round involving the leakage. We validate the existence of such a unique side-channel leakage through a set of experiments with a fully unrolled PRINCE cipher hardware, implemented on a field-programmable gate array (FPGA). In addition, we verify the validity and evaluate the hardware cost of a countermeasure for the unrolled implementation, namely the Threshold Implementation (TI) countermeasure.

Lightweight Cryptography (LWC) is suitable for IoTs which require a high level of security while keeping a low complexity. Many lightweight cryptographic algorithms have been proposed to satisfy these requirements. But there is currently no emerging standard concerning the symmetric block ciphering, as every algorithm has its own advantage. For instance one can be optimized for low latency, another one for low complexity but requires more rounds to be cryptographically secure to the detriment of throughput. Hence, a processor able to cope with all the algorithms should be ideal to provide agility, performance and security while keeping an affordable complexity. We present in this paper a specific execution unit of the RISC-V processor which is able to run the most common lightweight 64-bit block ciphers. The gain in performance can reach over a hundred compared to the reference architecture. The acceleration takes advantage of five specific instructions which can easily be adapted to the execution unit of a VexRiscv architecture. The complexity can double when implementing the new execution unit, but provide a high degree of agility and performance when executing most of lightweight cryptographic implementations.

This article proposes highly efficient Advanced Encryption Standard (AES) hardware architectures that support encryption and both encryption and decryption. New operation-reordering and register-retiming techniques presented in this article allow us to unify the inversion circuits in SubBytes and InvSubBytes without any delay overhead. In addition, a new optimization technique for minimizing linear mappings, named multiplicative-offset, further enhances the hardware efficiency. We also present a shared key scheduling datapath that can work on-the-fly in the proposed architecture. To the best of our knowledge, the proposed architecture has the shortest critical path delay and is the most efficient in terms of throughput per area among conventional AES encryption/decryption and encryption architectures with tower-field S-boxes. The proposed round-based architecture can perform AES encryption where block-wise parallelism is unavailable (e.g., cipher block chaining (CBC) mode); thus, our techniques can be globally applied to any type of architecture including pipelined ones. We evaluated the performance of the proposed and some conventional datapaths by logic synthesis with the NanGate 45-nm open-cell library. As a result, we can confirm that our proposed architectures achieve approximately 51-64 percent higher efficiency (i.e., higher bps/GE) and lower power/energy consumption than the other conventional counterparts.

An SR-latch can be regarded as primitive to build a True Random Number Generation (TRNG) or Physically Unclonable Function (PUF). Indeed, when the SR inputs of the latch are tied together and go from an unknown state (i.e. S=R=1) to a memory state (i.e. S=R=0), the behaviour depends on the balance between the NAND or NOR gates composing the latch. With the process mismatch, there is a great chance that the latch converges towards the same state, thus creating a PUF equivalent to a SRAM-PUF or latch-PUF. However, if the latch is well-balanced, it can enter a metastable state and converges to a stable state depending on the input noise, thus making a TRNG. In order to make sure some latches are able to behave like a TRNG, and some like a PUF, we consider a set of latches driven by the same SR signal. A test-chip in 28nm UTBB-FDSOI technology has been designed with 1024 latches in order to analyze the behavior. The FD-SOI technology enables easy change of the performances of gates using the body biasing, which consists in applying a specific body voltage to each gate. Hence, the two NOR gates composing the SR-latch can be tuned individually to get the optimality, i.e. the maximum entropy, for both PUF and TRNG. The results show that the optimal point is the same for both PUF and TRNG, and that the proposed structure can generate concurrently a PUF with high reliability, and a TRNG with high speed.

Probing attacks are serious threats on integrated circuits. Security products often include a protective layer called shield that acts like a digital fence. In this article, we demonstrate a new shield structure that is cryptographically secure. This shield is based on the lightweight block cipher and independent mesh lines to ensure the security against probing attacks of the hardware located behind the shield. Such structure can be proven secure against state-of-the-art invasive attacks. Then, we evaluate the impact of active shield on the performance of security IPs as PUF, TRNG, secure clock and AES using a set of fabricated ASICs with 65 nm CMOS technology of STMicroelectronics. Also, the impact of active shield on Side-Channel Attack (SCA) is evaluated.

This paper presents a practical implementation of all digital calibration algorithm for the gain and timing mismatches in undersampling Time-Interleaved Analog-to-Digital Converter (TI-ADC). A new Least Mean Square (LMS) based detection scheme is proposed to increase convergence speed as well as to enhance the estimate accuracy. Monte Carlo simulations for a four-channel undersampling 60 dB SNR TI-ADC clocked at 2.7 GHz show that SFDR can achieve approximately 90 dB SFDR within the stable point of the channel mismatch coefficients over the first three Nyquist Bands. The proposed architecture is implemented and validated on the Altera FPGA DE4 board. The synthesized design consumes a few percentages of the hardware resources of the FPGA chip and work properly on a Hardware-In-the-Loop emulation framework.

Conventional dual‐rail precharge logic suffers from difficult implementations of dual‐rail structure for obtaining strict compensation between the counterpart rails. As a light‐weight and high‐speed dual‐rail style, balanced cell‐based dual‐rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security‐sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)‐co‐processor is executed that is constructed on block random access memory (RAM)‐based BCDL in Xilinx Virtex‐5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non‐identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL.

The Tree-based FPGA offers better density and timing determinism than traditional mesh-based FPGA. Moreover, thanks to its multilevel structure, it offers greater easiness to balance dual signals in terms of routing resources number. In this paper, we study the use of the Wave Dynamic Differential Logic (WDDL) on a custom tree-based FPGA of 2048 cells. The WDDL technique offers an effective way to withstand Differential Power Attacks (DPA). However, the effectiveness of this countermeasure is guaranteed provided a symmetry is maintained between the routing of both the direct and complementary paths, which is very hard to achieve in FPGA. Thus, balancing aware Computer-Aided Design (CAD) tools must be developed. In this work, we propose first adjacent placement and balancing-aware routing techniques for tree-based FPGA to counter the routing unbalance. Then side channel analyses are performed on FPGA circuit implementing PRESENT crypto-processor. Experimental results show that the balancing methods enhance the design security against side channel attacks.

This paper presents the design methodology of a metastability-based True Random Number Generator (TRNG) on a Xilinx FPGA. As its structure is based on an open-loop delay chain, it provides both high throughput and security against physical attacks since it is not sensitive to coupling attacks as for oscillator-based TRNG. The proposed architecture, implemented in a Virtex-5 XC5VLX50T, uses 4% of the available resources and generates random bits at a 20~Mbps rate. This work gives a detailed description of the design methodology, more specifically the placement, routing and timing analysis of the TRNG structure. Also, the randomness quality of this TRNG has been validated using AIS-31 and NIST statistical tests.

In this paper we put forward a high-performance biometric fingerprint authentication algorithm for Match-On-Card (MOC) applications, compatible with the INCITS 378 and ISO/IEC 19794 standard. An efficient hardware implementation is proposed to adapt the algorithm for constrained embedded systems as smart cards. Time and memory complexities are reduced such that both integration and real time matching-on card can be met. The proposed architecture drops the required memory to 0.05% w.r.t. initial complexity, without any performance degradation. Therefore, the proposed solution is sufficient to meet the high level of security and the low computation time required in demanding authentication systems (e.g airports, electronic commerce and banking transactions).

In order to protect crypto-systems against side channel attacks various countermeasures have been implemented such as dual-rail logic or masking. Faults attacks are a powerful tool to break some implementations of robust cryptographic algorithms such as AES and DES. Various kind of fault attacks scenarios have been published. However, very few publications available in the public literature detail the practical realization of such attacks. In this paper we present the result of a practical fault attack on AES in WDDL and its comparison with its non-protected equivalent. The practical faults on an FPGA running an AES encrypt or are realized by under-powering it and further exploited using Piret's attack. The results show that WDDL is protected against setup violation attacks by construction because a faulty bit is replaced by a null bit in the cipher text. Therefore, the fault leaks no exploitable information. We also give a theoretical model for the above results. Other references have already studied the potential of fault protection of the resynchronizing gates (delay-insensitive). In this paper, we show that non-resynchronizing gates (hence combinatorial DPL such as WDDL) are natively immune to setup time violation attacks.