The video signal processor AxPe1280V has been developed forimplementation of different video coding applications accordingto standards like ITU-T H.261/H.263, and ISO MPEG-1/2.Itconsists of a RISC processor supplemented by a coprocessor forconvolution-like low-level tasks.RISC and coprocessor have beenimplemented in a standard cell design combined with full-custommodules.The processor was fabricated in a 0.5 µm CMOS technologyand has a die size of 82 mm{2}.It provides a peak performanceof more than 1 giga arithmetic operations per second (GOPS) at66 MHz.For processing of very computation-intensive algorithmsor high data rates, several processors can be bus-connected to forma MIMD multiprocessor system.

Interconnects must not only be analyzed with regard to opens and shorts but also with regard to the signal delays. Up to now, opens and shorts in bus systems on boards have been tested using boundary scan, mostly neglecting delay test. In addition, it has to be considered that the signal delay (i.e. the time when the signal crosses the switching threshold of the following gate) on a certain line within a bus system depends on the set of input signals of all bus lines. Furthermore, hazards can occur due to coupling between bus lines which can lead to an incorrect function of the whole circuit. Different interconnect systems with different test patterns have been analyzed and the results for 0.10 /spl mu/m technology will be given. The geometric data for the interconnects in 0.10 /spl mu/m technology has been derived or directly extracted from the SIA-Roadmap. With this data the line parameters for the simulation of the interconnects have been calculated with the help of a tool which takes into account conducting substrates.

A new method to integrate a test for CMOS address decoder open faults into March and pseudo random tests employed for testing semiconductor memories is presented. For commonly used memory organizations, March tests are implemented that, in addition to their original target faults, detect all CMOS address decoder open faults. The defection of these faults has been believed to require separate deterministic test patterns or tests of higher order. Address sequences generated by special complete LFSRs and address dependent data are utilized to alter March tests to detect all address decoder open faults and retain the detection properties of the original tests. The additional overhead in terms of silicon area for an on-chip realization of a built-in March test with the added fault detection features is negligible, and the test application time remains of O(N).

The SIA Roadmap shows a very aggressive drive to deep submicron designs. A significant corner stone in the industries' ability to utilize this tremendous capabilities is the usage of reusable cores. When employing cores, one must be sensitive to the quality of the interconnects which will carry signals between cores and the ASIC portion of the network. In this work we will use an extremely accurate line simulator which solves the transmission line equations derived from Maxwell's equations for the simulation of line systems. We will show that the coupling between bus lines is significant, since the signal delay can be increased and even hazards can occur. Furthermore, these effects depend on the set of input signals of all bus lines and the skew between the individual input signals. The lines' cross sections are taken from the SIA Roadmap going from 0.35 /spl mu/m technology design down to 0.10 /spl mu/m technology design.

The architecture and implementation of a programmable video signal processor dedicated as building block of a multiple instruction multiple data (MIMD)-based bus-connected multiprocessor system is presented. This system can either be constructed from several single processor chips, or it can be integrated on a large area integrated circuit containing several processors. The processor allows an efficient implementation of different video coding standards like H.261, H.263, MPEG-1 and MPEG-2. It consists of a RISC processor supplemented by a coprocessor for computation intensive convolution-like tasks, which provides a peak performance of more than 1 giga-arithmetic operations per second (GOPS). A large area integrated circuit integrating 9 processor elements (PE's) on an area of 16.6 cm/sup 2/ has been designed. Due to yield considerations redundancy concepts have been implemented, that-even in the presence of production defects-result in working chips utilizing a lower number of PE's. Each PE has built-in self-test (BIST) capabilities, which allow for an independent test of itself under the control of its integrated fault-tolerant BIST controller. Defective PE's are switched off. Only the PE's passing the BIST are used for video processing tasks. Prototypes have been fabricated in a 0.8 /spl mu/m complementary metal-oxide-semiconductor (CMOS) process structured by masks using wafer stepping with overlapping exposures. Employing redundancy, up to 6 PE's per chip were functional at 66 MHz, thus providing a peak arithmetic performance of up to 6 GOPS.