Medical imaging involves important computational geometric problems, such as image segmentation and analysis, shape approximation, three-dimensional (3D) modeling, and registration of volumetric data. In the last few years, Conformal Geometric Algebra (CGA), based on five-dimensional (5D) Clifford Algebra, is emerging as a new paradigm that offers simple and universal operators for the representation and solution of complex geometric problems. However, the widespread use of CGA has been so far hindered by its high dimensionality and computational complexity. This paper proposes a simplified formulation of the conformal geometric operations (reflections, rotations, translations, and uniform scaling) aimed at a parallel hardware implementation. A specialized coprocessing architecture (ConformalALU) that offers direct hardware support to the new CGA operators, is also presented. The ConformalALU has been prototyped as a complete System-on-Programmable-Chip (SoPC) on the Xilinx ML507 FPGA board, containing a Virtex-5 FPGA device. Experimental results show average speedups of one order of magnitude for CGA rotations, translations, and dilations with respect to the geometric algebra software library Gaigen running on the general-purpose PowerPC processor embedded in the target FPGA device. A suite of medical imaging applications, including segmentation, 3D modeling and registration of medical data, has been used as testbench to evaluate the coprocessor effectiveness.

Fingerprint classification is a key issue in automatic fingerprint identification systems. One of the main goals is to reduce the item search time within the fingerprint database without affecting the accuracy rate. In this paper, a novel technique, based on topological information, for efficient fingerprint classification is described. The proposed system is composed of two independent modules: the former module, based on Fuzzy C-Means, extracts the best set of training images, the latter module, based on Fuzzy C-Means and Naive Bayes classifier, assigns a class to each processed fingerprint using only directional image information. The proposed approach does not require any image enhancement phase. Experimental trials, conducted on a subset of the free downloadable PolyU database, show a classification rate of 91% over a 100 images test database using only 12 training examples.

Biometric recognition systems are rapidly evolving technologies and their use in embedded devices for accessing and managing data and resources is a very challenging issue. Usually, they are composed of three main modules: Acquisition, Features Extraction and Matching. In this paper the hardware design and implementation of an efficient fingerprint features extractor for embedded devices is described. The proposed architecture, designed for different acquisition sensors, is composed of four blocks: Image Pre-processor, Macro-Features Extractor, Micro- Features Extractor and Master Controller. The Image Pre- processor block increases the quality level of the input raw image and performs an adaptive binarization, introducing a novel hardware approach. The Macro-Features Extractor extracts singularity points. The Micro-Features Extractor extracts only micro-features around singularity points using an adaptive thinning and a post-processing phase to remove potential false micro-features. The Master Controller synchronizes and coordinates the two extractors. Xilinx ML507 board has been used to develop the prototype, while tests have been conducted on the PolyU (Hong Kong Polytechnic University) and the FVC2002 DB2-B free databases. These two databases have been chosen for their different characteristics in terms of image resolution and dimension in order to test the effectiveness of the proposed architecture. Experimental results show an interesting trade-off between used resources (about 32%) and fingerprint features extraction time (the lower execution time is 21.6 ms while the higher execution time is 28.4 ms, with a working frequency of 25 MHz), obtaining the best rate of false minutiae discharged of 5%.

User identification is a very interesting and complex task. Invasive biometrics is based on traits uniqueness and immutability over time. In forensic field, fingerprints have always been considered an essential element for personal recognition. The traditional issue is focused on full fingerprint images matching. In this paper an advanced technique for personal recognition based on partial fingerprint is proposed. This system is based on fingerprint local analysis and micro-features, endpoints and bifurcations, extraction. The proposed approach starts from minutiae extraction from a partial fingerprint image and ends with the final matching score between fingerprint pairs. The computation of likelihood ratios in fingerprint identification is computed by trying every possible overlapping of the partial image with complete image. The first experimental results conducted on the PolyU (Hong Kong Polytechnic University) free database show an encouraging performance in terms of identification accuracy.

Edge detection of color images is usually performed by applying the traditional techniques for gray-scale images to the three color channels separately. However, human visual perception does not differentiate colors and processes the image as a whole. Recently, new methods have been proposed that treat RGB color triples as vectors and color images as vector fields. In these approaches, edge detection is obtained extending the classical pattern matching and convolution techniques to vector fields. This paper proposes a hardware implementation of an edge detection method for color images that exploits the definition of geometric product of vectors given in the Clifford algebra framework to extend the convolution operator and the Fourier transform to vector fields. The proposed architecture has been prototyped on the Celoxica RC203E Field Programmable Gate Array (FPGA) board. Experimental tests on the FPGA prototype show that the proposed hardware architecture allows for an average speedup ranging between 6x and 18x for different image sizes against the execution on a conventional general-purpose processor. Clifford algebra based edge detector can be exploited to process not only color images but also multispectral gray-scale images. The proposed hardware architecture has been successfully used for feature extraction of multispectral magnetic resonance (MR) images.

Geometric or Clifford algebra (CA) is a powerful mathematical tool that offers a natural and intuitive way to model geometric facts in a number of research fields, such as robotics, machine vision, and computer graphics. Operating in higher dimensional spaces, its practical use is hindered, however, by a significant computational cost, only partially addressed by dedicated software libraries and hardware/software codesigns. For low-dimensional algebras, several dedicated hardware accelerators and coprocessing architectures have been already proposed in the literature. This paper introduces the architecture of CliffordALU5, an embedded coprocessing core conceived for native execution of up to 5D CA operations. CliffordALU5 exploits a novel, hardware-oriented representation of the algebra elements that allows for faster execution of Clifford operations. In this paper, a prototype implementation of a complete system-on-chip (SOC) based on CliffordALU5 is presented. This prototype integrates an embedded processing soft-core based on the PowerPC 405 and a CliffordALU5 coprocessor on a Xilinx XUPV2P Field Programmable Gate Array (FPGA) board. Test results show a 5× average speedup for 4D Clifford products and a 4× average speedup for 5D Clifford products against the same operations in Gaigen 2, a CA software library generator running on the general-purpose PowerPC processor. This paper also presents an execution analysis of three different applications in three diverse domains, namely, inverse kinematics of a robot, optical motion capture, and raytracing, showing an average speedup between 3× and 4× with respect to the baseline Gaigen 2 implementation. Finally, a multicore approach to higher dimensional CA based on CliffordALU5 is discussed.

The present work deals with modern computing systems security issues, focusing on biometric based asymmetric keys generation process. Conventional PKI systems are based on private/public keys generated through RSA or similar algorithms. The present solution embeds biometric information on the private/public keys generation process. In addition the corresponding private key depends on physical or behavioural biometric features and it can be generated when it is needed. Starting from fingerprint acquisition, the biometric identifier is extracted, cyphered, and stored in tamper-resistant smart card to overcome the security problems of centralized databases. Biometric information is then used for user authentication and for public/private keys generation. The initial trials have shown that the asymmetric keys generation distinctive power depends on biometric authentication accuracy, assuring unique asymmetric keys for each authenticated user.

Edge detection is one of the most used methods for feature extraction in computer vision applications. Feature extraction is traditionally founded on pattern recognition methods exploiting the basic concepts of convolution and Fourier transform. For color image edge detection the traditional methods used for gray-scale images are usually extended and applied to the three color channels separately. This leads to increased computational requirements and long execution times. In this paper we propose a new, enhanced version of an edge detection algorithm that treats color value triples as vectors and exploits the geometric product of vectors defined in the Clifford algebra framework to extend the traditional concepts of convolution and Fourier transform to vector fields. Experimental results presented in the paper show that the proposed algorithm achieves detection performance comparable to the classical edge detection methods allowing at the same time for a significant reduction (about 33%) of computational times.

Geometric or Clifford Algebra (CA) is a powerful mathematical tool that is attracting a growing attention in many research fields such as computer graphics, computer vision, robotics and medical imaging for its natural and intuitive way to represent geometric objects and their transformations. This paper introduces the architecture of CliffordCoreDuo, an embedded dual-core coprocessor that offers direct hardware support to four-dimensional (4D) Clifford algebra operations. A prototype implementation on an FPGA board is detailed. Experimental results show a 1.6x average speedup of CliffordCoreDuo in comparison with the baseline mono-core architecture. A potential cycle speedup of about 40x over Gaigen 2, a geometric algebra software library generator for general-purpose processors, is also demonstrated.

In recent years biological processes modelling and simulation have become two key issues in analyzing complex cellular systems. The computational requirements suggest to investigate alternative solutions to the common supercomputers and clusters in order to optimize and overcome computational bottleneck. The goal of this work is the design and the realization of an embedded processor for metabolic networks optimization in order to examine their behaviour and robustness under malfunctions of one or more nodes. The embedded processor has been prototyped on the Celoxica RC203E board, equipped with programmable FPGA technologies. A case studied outlining the E. Coli bacteria metabolic network is also presented.

Computer graphics applications require efficient tools to model geometric objects and their transformations. Clifford algebra (also known as geometric algebra) is receiving a growing attention in many research fields, such as computer graphics, machine vision and robotics, as a new, interesting computational paradigm that offers a natural and intuitive way to perform geometric calculations. At the same time, compute-intensive graphics algorithms require the execution of million Clifford operations. Clifford algebra based software intensive systems need therefore the support of specialized hardware architectures capable of accelerating Clifford operations execution. In this paper the architecture of CliffoSorII (Clifford coprocessor II), an embedded coprocessor that offers direct hardware support to Clifford algebra operations, is introduced. The coprocessor has been designed, implemented and tested on a Field Programmable Gate Array (FPGA) board. The experimental results show the potential to achieve a 20× speedup for Clifford sums and differences and a 5× speedup for Clifford products against the analogous operations in Gaigen, a standard geometric algebra software library generator for general purpose processors. An execution analysis of a ray tracing application is also presented.

Driver's drowsiness is stated as an important cause of road and highway accidents. Therefore, the development of a system for monitoring the driver's level of fatigue is desirable in order to prevent accidents. The paper presents the design and the implementation of a system able to find and evidence the drowsiness level of a driver in an ordinary motor vehicle, in order to prevent car accidents. The system, made up of a car installed infrared video camera connected to the Celoxica RC203E FPGA based board, is able to perform a real time video stream processing. The system exploits the “bright pupil” phenomenon produced by the retina, that reflects the 90% of the incident light when a radiation of 850 nm wavelength hit the retina itself. While acquiring the video, a processing chain is executed to detect driver's eyes and to compute a PERCLOS (Percentage of Eye Closure) function linked to the drowsiness level of a driver. The achieved experimental results show that an entire 720*576 frame processing requires only 16.7 ms, so that the system is able to perform real-time PAL video stream processing and has the potentiality to process 60 frames/sec. The effectiveness of the proposed drowsiness detection system has been successfully tested with a human subject in real operating condition, tracking driver's eyes and detecting drowsiness failures.

The main objective of this work is to analyze metabolic networks evolution in terms of their robustness and fault tolerance capabilities. In metabolic networks, errors can be seen as random removal of network nodes, while attacks are high-connectivity-degree node deletion aimed at compromising network activity. This paper proposes a software framework, namely BioAnalysis, used to test the robustness and the fault tolerance capabilities of real metabolic networks, when mutations and node deletions affect the network structure. The performed simulations are related to the central metabolic network of the well-known E. coli single-celled bacterium and involve either hub nodes or non-hub nodes, whose influence on the network robustness and activity is different. The performed trials have shown that the node connectivity degree as well as the node functional role in the network are key issues to evaluate the impact of node deletion on network robustness and activity. With more details, functional analysis has demonstrated that low-connectivity-degree nodes may drastically influence the normal behaviour of the network, while high-connectivity-degree nodes may produce soft failure in network operations. The results coming from described simulations have been confirmed by similar in vivo laboratory tests on real cluster of E. Coli bacteria.

Fingerprint classification and matching are two key issues in automatic fingerprint recognition. Generally, fingerprint recognition is based on a set of relevant local characteristics, such as ridge ending and bifurcation (minutiae). Fingerprint classification is based on fingerprint global features, such as core and delta singularity points. Unfortunately, singularity points are not always present in a fingerprint image: the acquisition process is not ideal, so that the fingerprint is broken, or the fingerprint belongs to the arch class. In the above cases, pseudo-singularity-points will be detected and extracted to make possible fingerprint classification and matching. As result, fingerprint processing involves few steps and, in the same way, fingerprint matching involves the comparison of few features with recognition rates comparable to the standard minutiae based systems. The experiments trials have been conducted on many official Fingerprint Verification Competition (FVC) databases. The achieved results show the effectiveness of the proposed approach, obtaining a False Acceptance Rate (FAR) = 1.22% and a False Rejection Rate (FRR) = 9.23% with FVC2002 DB2-A database. In the best of case, a FAR=0.26% and a FRR=7.36% with FVC2000 DB1-B database is achieved. To the best of our knowledge, this is the first recognition system based only on singularity regions.

The choice of hidden non-linearity in a feed-forward multi-layer perceptron (MLP) architecture is crucial to obtain good generalization capability and better performance. Nonetheless, little attention has been paid to this aspect in the ASR field. In this work, we present some initial, yet promising, studies toward improving ASR performance by adopting hidden activation functions that can be automatically learned from the data and change shape during training. This adaptive capability is achieved through the use of orthonormal Hermite polynomials. The “adaptive” MLP is used in two neural architectures that generate phone posterior estimates, namely, a standalone configuration and a hierarchical structure. The posteriors are input to a hybrid phone recognition system with good results on the TIMIT corpus. A scheme for optimizing the contributions of high-accuracy neural architectures is also investigated, resulting in a relative improvement of ~9.0% over a non-optimized combination. Finally, initial experiments on the WSJ Nov92 task show that the proposed technique scales well up to large vocabulary continuous speech recognition (LVCSR) tasks.

The basic aim of a biometric identification system is to discriminate automatically between subjects in a reliable and dependable way, according to a specific-target application. Multimodal biometric identification systems aim to fuse two or more physical or behavioral traits to provide optimal False Acceptance Rate (FAR) and False Rejection Rate (FRR), thus improving system accuracy and dependability. In this paper, an innovative multimodal biometric identification system based on iris and fingerprint traits is proposed. The paper is a state-of-the-art advancement of multibiometrics, offering an innovative perspective on features fusion. In greater detail, a frequency-based approach results in a homogeneous biometric vector, integrating iris and fingerprint data. Successively, a hamming-distance-based matching algorithm deals with the unified homogenous biometric vector. The proposed multimodal system achieves interesting results with several commonly used databases. For example, we have obtained an interesting working point with FAR = 0% and FRR = 5.71% using the entire fingerprint verification competition (FVC) 2002 DB2B database and a randomly extracted same-size subset of the BATH database. At the same time, considering the BATH database and the FVC2002 DB2A database, we have obtained a further interesting working point with FAR = 0% and FRR = 7.28% ÷ 9.7%.

Biometric recognition systems represent a valid solution to the safety problem of Internet accessibility, even if they do not always provide an environment easily comprehensible by users and operators with a mid-level of competence. This gap can be partially filled if, instead of using the conventional access routines to the authentication system, the user could simply write to the system through the interface and using high level sentences and requests be able to use its own natural language to reach the intended goal. On the other hand, biometrics features are widely used for recognition and identification all over the world, generating large databases.In this paper a user-friendly interface for the use and management of biometric recognition systems is proposed. The interface allows for a simpler and more natural access to the functionalities offered by biometric systems, increasing system usability. The interface allows for an intuitive parameterization of functions and procedures of system algorithms, for the optimized management of great databases by unspecialized operators. In addition, the interface addresses the fail-to-enrol issue, because the quality of the acquired fingerprint is computed at the acquisition time.

In this paper a new approach, based on iris micro-characteristics, has been used to make possible an embedded biometric extractor. This recognition approach is based on ophthalmologic studies that have proven the existence of different micro-characteristics as well as fingerprint minutiae. These micro-characteristics are permanent and immutable and they can be used to create strong and robust identification systems.Biometric recognition systems are critical components of our everyday lives. Since such electronic products evolve to software intensive systems, where software, becoming larger, more complex and prevalent, introduces many problems in the development phases. The development of embedded devices is one of the possible solutions to make possible reactive systems in the complex field of software intensive systems.The embedded micro-characteristics extractor proposed in this paper represents the first step to make available an embedded iris-based recognizer. The system has been prototyped on the Celoxica RC203E board, using hardware with programmable FPGA technologies and is able to perform iris processing and micro-characteristics extraction. The goodness of the proposed approach has been tested using an iris image from the CASIA database. The considered iris micro-characteristics are nucleus and collarette and the execution time to extract them is about of 1.1 seconds.

In this paper a novel embedded fingerprints authentication system based on core and delta singularity points detection is proposed. Typical fingerprint recognition systems use core and delta singularity points for classification tasks. On the other hand, the available optical and photoelectric sensors give high quality fingerprint images with well defined core and delta points, if they are present. In the proposed system, fingerprint matching is based on singularity points position, orientation, and relative distance detection. As result, fingerprint matching involves the comparison between few features leading to a very fast system with recognition rates comparable to the standard minutiae based recognition systems. The whole system has been prototyped on the Celoxica RC203E board, equipped with a Xilinx VirtexII FPGA. The prototype has been tested with the FVC databases. Hardware system performance show high recognition rates and low execution time: FAR = 1.2% and FRR=2.6%, while each fingerprint elaboration requires 34.82 ms. Considering both FAR, FRR indexes and the high speed, the proposed system could be used for identification tasks in large fingerprint databases. To the best of our knowledge, this is the first authentication system based on singularity points.

Automatic vehicle driving involves several issues, such as the capability to follow the road and keep the right lane, to maintain the distance between vehicles, to regulate vehiclepsilas speed, to find the shortest route to a destination. In this paper a real-time automatic lane-keeper is proposed. The main features of the system are the lane markers location process as well as the computation of the vehiclepsilas steering lock. The above techniques require high elaboration speed to execute, check and complete an operation before a prearranged time. Clearly if system processing exceeds the deadline, the whole operation became meaningless or, in the meantime, the vehicle can reach a critical condition. The proposed system has been prototyped using the Celoxica RC203 board, equipped with a Xilinx Virtex II FPGA, for real-time processing of real motorway scenes coming from aCCD camera on a moving vehicle. The required processing time is 25,521 ms per frame, so that the system could process 39 frames/sec. Vehiclepsilas steering lock is computed with an average error of plusmn 2.5deg.

Geometric or Clifford algebra is an interesting paradigm for geometric modeling in fields as computer graphics, machine vision and robotics. In these areas the research effort is actually aimed at finding an efficient implementation of geometric algebra. The best way to exploit the symbolic computing power of geometric algebra is to support its data types and operators directly in hardware. However the natural representation of the algebra elements as variable-length objects causes some problems in the case of a hardware implementation. This paper proposes a 4D Clifford algebra in which the variable-length elements are mapped into fixed-length elements (quadruples). This choice leads to a simpler and more compact hardware implementation of 4D geometric algebra. The paper also presents the architecture of CliffArchy, a coprocessing core supporting the new fixed-length Clifford operands. A prototype implementation on a FPGA board is described.

Computer graphics applications require efficient tools to model geometric objects. The traditional approach based on compute-intensive matrix calculations is error-prone due to a lack of integration between geometric reasoning and matrix-based algorithms. Clifford algebra offers a solution to these issues since it permits specification of geometry at a coordinate-free level. The best way to exploit the symbolic computing power of geometric (Clifford) algebra is supporting its data types and operators directly in hardware. This paper outlines the architecture of S-CliffoSor (Sliced Clifford coprocessor), a parallelizable embedded coprocessor that executes native Clifford algebra operations. S-CliffoSor is a sliced coprocessor that can be replicated for parallel execution of concurrent Clifford operations. A single slice has been designed, implemented and tested on the Celoxica Inc. RC1000 board. The experimental results show the potential to achieve a 3times speedup for Clifford sums and 4times speedup for Clifford products compared to against the analogous operations in the software library generator GAIGEN.

Multi-agent systems expose users to risks related to lack of knowledge above interacting users. Such systems should provide tools to protect their own resources from illegal accesses by unauthorized users. This paper describes a security framework for multi-agent systems preventing a trusted agent to interact with malicious agents and granting agent and platform resources. This feature is obtained adding an access control mechanism that joins the benefits of credential based access control, role based access control and mandatory access control. Authorizations and access control policies are set by XML based policy files. A case study on a distributed document retrieval system is also illustrated.

Event detection is a fundamental yet critical component in automatic speech recognition (ASR) systems that attempt to extract knowledge-based features at the front-end level. In this context, it is common practice to design the detectors inside well-known frameworks based on artificial neural network (ANN) or support vector machine (SVM). In the case of ANN, speech scientists often design their detector architecture relying on conventional feed-forward multi-layer perceptron (MLP) with sigmoidal activation function. The aim of this paper is to introduce other ANN architectures inside the context of detection-based ASR. In particular, a bank of feed-forward MLPs using sinusoidal activation functions is set up to address the event detection problem. Experimental results demonstrate the effectiveness of this ANN design for speech attribute detectors

The efficiency and the accuracy of a digital feedforward neural networks must be optimized to obtain both high classification rate and minimum area on chip. In this paper an efficient MLP digital implementation. The key features of the hardware implementation are the virtual neuron based architecture and the use of the sinusoidal activation function for the hidden layer. The effectiveness of the proposed solutions has been evaluated developing different FPGA based neural prototypes for the high energy physics domain and the automatic road sign recognition domain. The use of the sinusoidal activation function decreases hardware resource employment of about 32% when compared with the standard sigmoid based neuron implementation. The virtual neuron implementation makes efficient the mapping of a neural network into hardware devices since it leads to a significant decreasing of concurrent memory access.

Image and video processing tasks are often confined for real-time execution on large size workstations or expensively custom designed hardware. The current availability of mature reconfigurable hardware, like field programmable gate arrays (FPGAs), coupled with the usage of hardware programming languages offers a good path for porting such applications on portable devices. This paper explores the rapid prototyping of a real-time road sign recognition system on a FPGA, using an algorithmic-like hardware programming language: the Handel-C language. We investigate the relationship between efficient Handel-C data, structures, constructs and the related high level C data, structures, constructs. Programming guidelines are proposed for the development of real-time image and video processing, starting from a better organized high level C code that can be then easily ported in Handel-C. Results are illustrated showing the effectiveness of employing Handel-C to turn an entirely software based system into a fully functional field deployable device.

Abstract only given. A significant amount of current research on vector quantization (VQ) implementations addresses increasing the speed of image encoding. This is typically accomplished by imposing structures, exploiting properties of the distance measure, or developing efficient and fast implementations. This research proposes a parallel implementation of a full-search VQ encoding algorithm using a low memory, fine grain SIMD pixel processor (SIMPil) being developed at Georgia Tech. This implementation fully exposes the available parallelism of the encoding process and exploits the processing and I/O capabilities of the processor, resulting in a system that can perform real-time image and video compression. The proposed implementation encodes a large region of the original image at once, replacing each constituent input block with its corresponding VQ codeword index. Preliminary simulation results indicate that the proposed implementation is capable of sustain real-time frame rates. In the simulation, 92058 clock cycles are required to encode a single 64/spl times/64 region. The image of Lena (256/spl times/256) requires 16 passes to be completely encoded, for a total of about 1472089 clock cycles. With a 50 MHz processor, a 256/spl times/256 image frame will be encoded in 29.4 ms, supporting a frame rate of >30 frames/sec. Three VQ implementations are compared on different hardware platforms. A prototype SIMPil implementation is being fabricated by MOSIS in 0.8 /spl mu/m CMOS.